IORD_16DIRECT causes 2 reads on a 16-bit data bus

Altera_Forum · ‎06-24-2005

A 16-bit write quite rightly performs a single write cycle. A 16-bit read performs two reads, with the next (word) address being read on the second cycle.

Why? Simplification of the bus arbiter?

Altera_Forum · ‎06-24-2005

Hi JasonDiplomat,

I hope you don't mind me tagging a question onto your post, but I also have this problem, but with 8-bit access and was about to start a post.

Using Quartus/Nios V5.0, and a Nios II/e CPU, I have created a component as an 8-bit avalon_tristate_slave in Memory slave mode.

When accessing this component, writes take a single bus cycle, but reads, take 4 consecuive cycles, reading from BASE to BASE + 3.

Simple code example:

volatile alt_u8 Test = 0;

*(volatile alt_u8*)BPIO_BIDIR_BASE = Test; // Takes 1 bus cycle (as expected)

Test = *(volatile alt_u8*)BPIO_BIDIR_BASE; // Takes 4 bus cycles (NOT as expected)

This does not seem logical

Can anyone explain what is going on here?

Altera_Forum · ‎06-24-2005

Hello,

Searching the forum with the keywords „dynamic AND bus AND sizing” will help to understand the behaviour. Take the Avalon bus specification as a book with golden rules.

Regards,

niosIIuser

Altera_Forum · ‎06-28-2005

Hi, JasonDiplomat

I confuesd the same problem, please see create a new componet(avalon tristate) (http://www.niosforum.com/forum/index.php?act=st&f=2&t=1984) POST 2