My starting point was a project for the Trenz CYC1000 which couples a Cyclone 10 LP with a 64M bit SDRAM memory chip. I'm successfully developing and running a NIOS2 application but the performance is really poor and I need more throughput. A quick look at the linker settings shows that all sectors are going into SDRAM, which will kill performance for sure. I tried:
Putting .text into the 16kB of on chip memory but it didn't fit.
Putting .bss and/or .rwdata into the 16kB of on chip memory but the exception handling code wont span some jumps. The error code is "warning: unable to reach alt_instruction_exception_handler (at 0x2a0) from the global pointer (at 0x1028ad8) because the offset (-16943160) is out of the allowed range, -32678 to 32767"
What can I do? I guess I'd really like to know what this offset limit means in practice.
Thanks for that. I've looked at the description of mgptop and I'm not really any the wiser. In the mean time I've got it to link by putting onchip memory just below the SDRAM so there aren't big gaps in memory space. There look to be a lot of settings that should improve performance (e.g. separate interrupt stack) but I'm guessing a lot of them may also just break the project. I'm reluctant to change anything I don't really understand.
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Hi,
Greetings and welcome to Intel's forum.
This error usually indicates that you exceed the amount of space allowed for global variables.
You may try to open the BSP in the BSP editor and set mgpopt to local in the GUI. Regenerate the BSP and recompile your project and it should be able to work.
-mgptop=global should be in the makefile CFLAGS by default and should just be able to change it to mgpopt=local.
Hope to hear on your feedback. Thank you
Regards,
Kelly
Thanks for that. I've looked at the description of mgptop and I'm not really any the wiser. In the mean time I've got it to link by putting onchip memory just below the SDRAM so there aren't big gaps in memory space. There look to be a lot of settings that should improve performance (e.g. separate interrupt stack) but I'm guessing a lot of them may also just break the project. I'm reluctant to change anything I don't really understand.
Hi,
Thank you for your response. I agree with your statement as it changes the algorithm behind that you do not understand.
Anyway, is linking onchip memory just below the SDRAM the workaround to bypass the issue?
Hope to hear on your feedback.
Thank you.
Regards,
Kelly
Yes, I could put .bss, .stack and .rwdata in onchip RAM and throughput has improved significantly to where it needs to be. I think what I will try is switching to the 'full fat' NIOS2 as that includes caches, which is what I really need. It's a shame there's not a bit more granularity in some of these options.
Hi,
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Thank you.
Regards,
Kelly Jialin. GOH
Hi,
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Thank you.
Regards,
Kelly Jialin, GOH
