Interacting with NIOS II Processor

[Altera_Forum]

Hi there, 

 If a Nios II processor needs to control the rest of FPGA logic through a set of registers and also monitor the status through another set of registers, what is the preferrable way of interacting between the Nios II and the other FPGA logic?  Should I use PIO to simulate a parallel bus to read/write all the registers? i.e. for wirte operation: write a register address for the FPGA logic to decode and then write register value.   Or, since we have so much interconects available on FPGA, should I just assign a PIO for each registers and use IRQ to signal the change of input register values?  Thanks, Hua

[Altera_Forum]

Hello, 

 To interface custom logic with the Nios II Processor, the best way is to use an Avalon Interface. See the Avalon Interface Specification for detailed explanation (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf). There are different types of interface defined (Memory Mapped, Streaming, ...), and according to what you said, you would use the Avalon Memory Mapped and Conduit.  Look at the specification, and if you still have interrogation, ask.  Jérôme

[Altera_Forum]

depending upon what the rest of the fpga is you have 2 ways to implement that 

1. you can create an sopc component that holds the rest as included modules 2. you can create an sopc component that just connects to avalon and holds only those control registers and status registers, but all signals go out of your sopc module to top level and you do those connections there.  both methods have there postive and negative sides.  with both methods you won't need to restart the sopc builder again as long as the avalon interface between avalon switch fabric and your custom ip does not change.

[Altera_Forum]

Thank you all for your reply! I will do more readings toward the directions you suggested and will come back with questions if I have any.

[Altera_Forum]

In my opinion, the fast way is to read sopc_ip.  

C:\Altera\91\ip\altera\sopc_builder_ip

[Altera_Forum]

--- Quote Start ---   2. you can create an sopc component that just connects to avalon and holds only those control registers and status registers, but all signals go out of your sopc module to top level and you do those connections there.   --- Quote End ---    Hi MSchmitt,  I have implemented the second method in your post. It looks pretty good from here. But you mentioned that "both methods have their postive and negative sides", could you please elaborate on the downside of method 2 a little bit more? Thanks!  Another question I have on this custom component is the interrupt handling mechanism. In my module I created a register to allow a Nios II processor enabling/clearing the interrupt through avalon slave interface, and I can see in the future I may have to create a interrupt vector register to show which event(s) trigger(s) the interrupt. I am wondering if there is a IP available already for handling these type of operations.  Thanks, Hua

[Altera_Forum]

Also, I got the impression that the avalon interface will handle the clock domain boundary automatically. Is it true for the following scenario? 

 Let's say all the registers will be used in a different clock domain (clk1) from the avalon mm master interface (i.e. Nios II core, on clk0 domain), is it ok for me to associate my avalon mm slave with clk1 domain and use those registers in clk1 domain trouble free?  Thanks, Hua

[Altera_Forum]

--- Quote Start ---  In my opinion, the fast way is to read sopc_ip.  C:\Altera\91\ip\altera\sopc_builder_ip  --- Quote End ---    Thanks and agreed.