Is HW breakpoint required for SW breakpoint ?

[PTrig]

Hi,

I am trying to add breakpoints to my Nios II Eclipse debug session.

My HW system has not defined any HW breakpoints or Data break points (both explicitly set to 0) in Quartus Platform Design stage. Data triggers also set to 0. Trace type "none".

Jtag debug included, but debugreq and debugack signals NOT included.

In BSP settings:

Allow code at reset is enabled.

alt_load() is enabled.

There's NO rodata or rwdata copy selected for alt_load() during alt_main(). 

bsp_cflags_debug has option "-g" enabled.

OC ram only has reset and exceptions [via alt_load()]. All of my .text and other code is in Off Chip ddr2 RAM. The code is executed from this Off chip RAM. Reset vector however, points to OC ram which has reset, followed by exceptions.

When I try to add a breakpoint, the debug perspective shows errors.

"cannot access memory at <address> " and "failed to add breakpoint".

The <address> to be accessed is in the Off chip RAM location.
The code flow only stops once at main() and that's it.

From all the documentation, forum search and literature, I could not figure out why this error occurs. The address location in memory is off chip RAM but is R/W (volatile). Hence theoretically, the debugger should be able to insert a software breakpoint instruction. I am NOT debugging boot code and whatever code is present is in R/W memory.

In all the user guides, sw dev handbook, embedded handbook and the IP guide, it is stated that HW breakpoints are needed for boot code debug (non volatile memory, instructions cannot be inserted/overwritten.

If HW breakpoints are needed for SW breakpoints, I have not found it in literature.  Of course, there's something else, since the breakpoint is not set.

What am I missing (even theoretically)? 

Any other setting(s) to check/set ?

Unfortunately, cannot share any files.

Thanks in advance !

Edit 1 - HW is Cyclone 5

Edit 2 - updated Off Chip RAM as volatile in description

[EBERLAZARE_I_Intel]

Hi,

Is your Hardware and Software build okay? Hardware = Quartus compilation, Software from BSP > .elf/.hex generation.

If there are any error can you share the screenshots of them?

For debug I do the following:

https://www.intel.com/content/www/us/en/docs/programmable/683282/current/debugging-the-project-on-nios-ii-hardware.html

Then would just check the main.c and set the breakpoints, or observe the memory, dissembly etc.

[PTrig]

Hi,

Thanks for your response !

The HW is built and the BSP generation is correct, since this setup has existed for some time now in existing solutions.

I have followed the steps that you shared and the debug stops before main() as is illustrated.
However, no further breakpoints are added and I am not able to use the "run to line" feature either (with similar errors as in original post).

Again, the memory that has the code is external OFF chip RAM (as defined in linker memory regions).

This is below the reset/exceptions address in the address space for the Nios II. 

Attached are some console/ disassembly (trying to select stepping mode for the suspended thread (at main()).

Another screenshot has the current break at main() marked in RED.

So the question is, how to add breakpoint to off chip code, with no hardware support. Is a SW breakpoint possible?

Thanks !

[EBERLAZARE_I_Intel]

Hi,

Thanks for the screenshots, let me check them out. I will get back to you.

[EBERLAZARE_I_Intel]

Hi,

[EBERLAZARE_I_Intel]

could you capture a screenshot of your Linker Script of your BSP settings?

The one with the addresses in the "Linker Script" tab in the BSP GUI?

[EBERLAZARE_I_Intel]

Hi,

Any update from your side?

[PTrig]

Hi,

Thanks for the follow up!

I'm afraid I cannot share any files or screenshots. 

I will try to find a solution, but I cannot modify the project too much, especially regarding the memory layout. I will have to play around with the BSP, but I am looking for a theoretical solution or reasoning as to why a breakpoint is not able to be set.

I see the following possible issues:

1. Memory address that has the code to break is Off chip ddr2 and resides below the reset vector (nothing I can do about this). I read in some documentation that NIOS2 cannot view memory below its reset address. 

2. debugack, debugAckReq, cpureset_req signals are not included. I may be able to experiment with that.

3. HW breakpoint and data trace need to be instantiated and non zero (that's my original question).

My setup: I boot from config flash QSPI (micron), alt load runs the pre-boot loader, the pre-loader copies the application image from qspi to off chip ddr2 ram (off chip), and then jumps to execution on off chip ram. All my main() code and other code(s) are in this off-chip ram and below the reset vector.

.reset is at ON chip RAM, followed by .exceptions.

If there's nothing theoretically that can be suggested, or if there are particular questions, I may be able to check or answer.

Otherwise, you may snooze this thread for now. I will update here if I am able to make progress.

Thanks so much for your support!

[EBERLAZARE_I_Intel]

Hi,

Maybe we can get back to your usual Nios II boot flow.

So, when you program the .sof, could you run/program the Nios II ".elf" after? Meaning you can run the Nios II and see all the output prints or your design is functioning.

Or is your design is not properly functioning after programming the .elf?

[PTrig]

Hi,

Thanks for your efforts!

The design is well established for many years (and works flawlessly), I am new to this codebase and trying to step through to learn the code and logic. I could do printf(), but that's not good enough, I need to step through and have a look at registers, etc.

The design compiles and loads to the HW. Everything works fine. 
I am trying to add breakpoint to step through the Application code and am not able to. Upon further investigation, I found the details as shared above, and will try to regenerate bsp(keeping the sof file constant), and if that doesn't work, will regenerate HW sof files with HW breakpoint and traces added, to see if that works.

I will update here with the results, and if I am able to make it break.

The details already shared are probably most I can share.

Thanks again!

[EBERLAZARE_I_Intel]

Hi,

Yea, if the Nios programming is working, then we may be able to read some of the memory in the memory tab console, when we "program the Nios" to the board, meaning after programming the .sof, then something like start to view memory browser when we download the elf file, we may be able to see something, but I need sometime to look into this particular step.

Anyway, I will be back after Christmas around 27th, will get back to you then.

[EBERLAZARE_I_Intel]

Hi,

Any new update from your side?

You could check these debug signals for JTAG, not sure if that would help:

https://www.intel.com/content/www/us/en/docs/programmable/683836/current/reset-and-debug-signals.html

https://www.intel.com/content/www/us/en/docs/programmable/683836/current/jtag-debug-tab.html

[PTrig]

Hi,

Thanks for your continued efforts! Hope you had a great holiday season and wishing you a very happy new year 2024!

I think we may be moving in the correct direction now.

As shared before, these signals are NOT included in the design (attached screenshots)

Are these required for SW breakpoints?

I will try and regenerate the HW with these included.

Thanks for the documentation you linked to.

[PTrig]

Hi,

I found the classic processor reference page:

4.5.1. Debug Level Settings (intel.com)

What I'm looking for is, to get equivalent to level 1 for the new nios2 processor.

Do I need to enable something ? From the table, I should not need any debug_req or other signals. 
Does using the Run/Debug config (v2 beta nios) automatically work? I have not tried the v2 beta hardware configuration for run/ debug.

Is there a way to do this?

Thanks!

[EBERLAZARE_I_Intel]

Hi,

Allow me sometime to check on that, I will get back to you.

[EBERLAZARE_I_Intel]

Hi,

Is your Nios II the "Nios II/e Core":

If it is, then the JTAG debug module on the Nios II/e core does not support hardware breakpoints or trace:

https://www.intel.com/content/www/us/en/docs/programmable/683836/current/jtag-debug-module-10059.html

[EBERLAZARE_I_Intel]

Hi,

Do you have any update?

[EBERLAZARE_I_Intel]

Hi,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[PTrig]

Hi,

I am unwell, hence the delay.

My project is "Nios II/f core". As stated earlier, I am not looking for Hardware Breakpoints. Only looking for SW breakpoints and the minimum settings required for it.

Thanks !