Is it possible to run NIOSV through SDRAM ?

[himanshuvaria]

Hello, 

I am developing a project where NIOS II needs to replaced with NIOSV processor. When my design was having NIOS II as CPU, I was running the software code through External SDRAM on the Cyclone IV E Kit(EP4CE40F23C8). It's working fine with NIOS II. Able to run the software program.

Now, when I replaced the NIOS II processor with the NIOSV processor, I am not getting the expected results. I am trying to print a Simple "Hello World" code through the NIOSV processor with the same configuration of design. Almost all BSP settings are same for NIOSV processor as of the NIOS II. Still not getting the results.

When running the NIOSV from On-Chip-Ram, everything works as expected, but when I try to run the NIOSV through external SDRAM, the code does not gets executed as expected.

I want to inquire that if we can run the NIOSV processor through external SDRAM or not ?

Please note that I am not talking here about booting the NIOSV. I am simply running the software image through RiscFree IDE software on the external SDRAM of the board.

Regards,

Himanshu

[himanshuvaria]

Sure. Would be waiting for your response

[himanshuvaria]

Hello,

Did you follow up on the issue ? Please share your response !!

[EBERLAZARE_I_Intel]

Hi again,

For this issue, we currently working on a fix, we will update you from time to time, this will take some time. 

We will follow-up with the thread below you filed recently and proceed to close this thread.

https://community.intel.com/t5/forums/forumtopicpage/board-id/nios-II-embedded-design-suite/message-id/52189#M52189

[Moffo]

Hi Himanshu,

     Greetings.

   I am first wondering how you succeeded to have the sdram controller in the platform designer. Please what version of Quartus are you using? I am using here Quartus Prime 22.1.2 standard edition (the latest version) there’s no more the “sdram controller” in the platform designer.

  So I wanted also to make one of my designs that is using nios II running in nios-v through external sdram but I got stuck on adding the sdram controller in qsys because it is missing.

Please any assistance.

Thanks

[himanshuvaria]

Hi,

I know that SDRAM Controller IP is no more supported in the latest Quartus Versions. But I would like to inform you that I have the .TCL file that will generate source of SDRAM Controller IP and it's path is added in the user_components.ipx file. The .TCL will show the SDRAM Controller IP in the QSYS system. It is an older version of SDRAM Controller IP which I am using. 

The SDRAM Controller IP, which I am using is from older Quartus 18.x version. To use in the latest Quartus Versions, we need to add the .TCL file in the IP_IPX_PATH variable which have file user_components.ipx.

You can ask INTEL to provide the TCL of the SDRAM Controller IP,

Regards,

Himanshu

[Moffo]

Hi Himanshu,

Thanks for the reply.

I will follow your instructions and bring you feedback about the use of the sdram with nios-v.

[JingyangTeh]

Hi

Since there is a duplicate case for this issue, we will follow up this issue in the case link below:

https://community.intel.com/t5/forums/forumtopicpage/board-id/nios-II-embedded-design-suite/message-id/52189#M52189

I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.

Regards

Jingyang

[Vincent_F]

Dear Himanshu,

Did you finally manage to run your program on the SDRAM? I also managed to include the SDRAM Controller Intel FPGA IP in Quartus 23.1. Compilation goes well but, like you, the basic "Hello World!" program gets stuck with SDRAM when it works fine with on-chip RAM. Yet, I can't run my project's software on the on-chip memory because the required amount of RAM won't fit on the FPGA.

Also, I would be interested in seeing how you worked around the interface issue for the exported signals. I had to rewrite the conduit interface ports for each signal individually.

Finally, do you have any idea who I could contact at Intel's to provide me with a more compatible version of the SDRAM Controller IP? I tried to contact Intel's support, but I can't find any section related to FPGAs. Probably, I looked in the wrong place...

Thanks in advance for your help.

Looking forward to reading from you.

Best regards

Vincent

[monkstein]

Hi @Vincent_F , 

I think I have a solution for you if you are still experiencing the problem. Just DM me or write here - I'll share a link if needed.