JPEG core with NiosII

[Altera_Forum]

Hi Every body 

i am working on project : JPEG core on FPGA  Probably i will use NiosII development kit with STRATIX board and i will iterface the JPEG core with the NiosII as a new component so is this feasible? please give some suggest and help tanks

[Altera_Forum]

Here is a good place to start reading: http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp (http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp) 

 You will want to pay attention to the documents about component editor, developing components, and the Avalon memory mapped interface specification.  What you are attempting is feasible. I don't know anything about your JPEG core but if it is high performance be sure to stuff data into it using a direct memory access (DMA) engine.  I hope that helps get you started

[Altera_Forum]

Thanks for the information, 

but the main purpose of this project is to ameliorate the previous works concerning JPEG decoder and all related projects, so in reality i want to speed up and accelerate the algorithm by implementing hardware blocks such as DCT, IDCT, Huffmann, Quantifier... interfaced with Nios.

[Altera_Forum]

--- Quote Start ---  originally posted by melomane@Dec 22 2006, 08:17 AM thanks for the information, but the main purpose of this project is to ameliorate the previous works concerning jpeg decoder and all related projects, so in reality i want to speed up and accelerate the algorithm by implementing hardware blocks such as dct, idct, huffmann, quantifier... interfaced with nios. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20187)  --- quote end ---    --- Quote End ---    Maybe you should check thejpeg compressor core (http://www.opencores.org/projects.cgi/web/jpeg/overview) from opencores.  Avishay

[Altera_Forum]

Thanks for the information it&#39;s very important for me 

but sorry i still have a question : How can i display the image in format JPEG after compressing it with my own JPEG compressor?

[Altera_Forum]

--- Quote Start ---  originally posted by melomane@Dec 26 2006, 08:37 AM thanks for the information it&#39;s very important for me but sorry i still have a question : how can i display the image in format jpeg after compressing it with my own jpeg compressor? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20216)  --- quote end ---    --- Quote End ---    Somehow transfer it to a PC. A flash card, a serial link.  I&#39;m currently working on a JPEG decoder, based on the reference implementation of the Indepedant JPEG Group. I&#39;m developing a few specific hardware accelerators; I have found that memory bandwidth is a major bottleneck (I also have a LCD controller that takes up quite some bandwidth http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif )  For example, my hardware Avalon MM IDCT core takes only 20 or so clock cycles to compute a full 8x8 IDCT including dequantization/descaling/rounding/clamping, but just transferring the coefficients and the resulting pixels components takes many more cycles (195 cycles just to load 64 coefficients in 32 writes (no looping), with a tightly coupled instruction and data memory). In the software version, these transfers took only a small percentage of the total computation time, but now it has become a major bottleneck. (I already have devised another way to speed this up).  Now I have sped up the IDCT, upsampling has become the major bottleneck, taking up over 60% of the total time, as this is basically just data copying.   My goal is to decode a 640x480 4:2:0 file in 100ms, though I think this isn&#39;t a realistic goal unless I use a full hardware JPG decoder http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif (it&#39;s around 550ms now)  I wonder if it&#39;s useful to use SDRAM, as currently I use the Async SRAM on a Nios development kit/Cyclone edition.

[Altera_Forum]

--- Quote Start ---  originally posted by jeroen+dec 27 2006, 11:45 pm--><div class='quotetop'>quote (jeroen @ dec 27 2006, 11:45 pm)</div>  --- quote start ---  <!--quotebegin-melomane@Dec 26 2006, 08:37 AM thanks for the information it&#39;s very important for me but sorry i still have a question : how can i display the image in format jpeg after compressing it with my own jpeg compressor? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20216)  --- quote end ---    --- Quote End ---    Somehow transfer it to a PC. A flash card, a serial link.  I&#39;m currently working on a JPEG decoder, based on the reference implementation of the Indepedant JPEG Group. I&#39;m developing a few specific hardware accelerators; I have found that memory bandwidth is a major bottleneck (I also have a LCD controller that takes up quite some bandwidth http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif )  For example, my hardware Avalon MM IDCT core takes only 20 or so clock cycles to compute a full 8x8 IDCT including dequantization/descaling/rounding/clamping, but just transferring the coefficients and the resulting pixels components takes many more cycles (195 cycles just to load 64 coefficients in 32 writes (no looping), with a tightly coupled instruction and data memory). In the software version, these transfers took only a small percentage of the total computation time, but now it has become a major bottleneck. (I already have devised another way to speed this up).  Now I have sped up the IDCT, upsampling has become the major bottleneck, taking up over 60% of the total time, as this is basically just data copying.   My goal is to decode a 640x480 4:2:0 file in 100ms, though I think this isn&#39;t a realistic goal unless I use a full hardware JPG decoder http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif (it&#39;s around 550ms now)  I wonder if it&#39;s useful to use SDRAM, as currently I use the Async SRAM on a Nios development kit/Cyclone edition. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20245)</div> [/b]  --- Quote End ---     Thank you Jeroen for your useful information and I think you have done a very good work even the speed up of the software version did not satisfied you. In previous work i have speed up an algorithm which treats the 3D images with a lot of multiplier  adder, and divide. These macroblocs, i have integrated it with two modes : first as custom instructions, and then as new component interfaced with NiosII processor As a result i have speed up the software version taking over 70%(Version full custom instructions). For the "Component version" i met some difficulties in interfacing my Hardware accelerators with Avalon Bus so I abort this solution http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif . Please if you have some samples of Interfaces to Avalon (VHDL language in preference) in order to add my accelerators as new component. Send it to me and I will be very grateful to you http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif   The device targeted is the stratixII (Simulated on Stratix professional Borad) and i have not tried to display some images before.

[Altera_Forum]

--- Quote Start ---  originally posted by melomane@Dec 28 2006, 09:57 AM for the "component version" i met some difficulties in interfacing my hardware accelerators with avalon bus so i abort this solution http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/unsure.gif .  --- Quote End ---    What specific problems do you have with designing Avalon MM hw accelerators? Avalon interfacing is very simple.

[Altera_Forum]

--- Quote Start ---  originally posted by jeroen+dec 28 2006, 11:12 am--><div class='quotetop'>quote (jeroen @ dec 28 2006, 11:12 am)</div>  --- quote start ---  <!--quotebegin-melomane@Dec 28 2006, 09:57 AM  for the "component version" i met some difficulties in interfacing my hardware accelerators with avalon bus so i abort this solution http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/unsure.gif .  --- Quote End ---    What specific problems do you have with designing Avalon MM hw accelerators? Avalon interfacing is very simple. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20256)</div> [/b]  --- Quote End ---   Yes, First i&#39;m working with QuartusII 5.0 (SOPC builder) And for my specifc problems : For example my hardware accelerator needs a data as entry much longer than 32 bits so can i do? especially when the data needs to be available at a specific clock cycle.

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

--- Quote Start ---  originally posted by jeroen+dec 29 2006, 01:53 am--><div class='quotetop'>quote (jeroen @ dec 29 2006, 01:53 am)</div>  --- quote start ---    --- quote start ---  originally posted by melomane@dec 28 2006, 02:47 pm   --- quote start ---  originally posted by jeroen@dec 28 2006, 11:12 am <!--quotebegin-melomane@Dec 28 2006, 09:57 AM  for the "component version" i met some difficulties in interfacing my hardware accelerators with avalon bus so i abort this solution http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/unsure.gif .  --- Quote End ---    What specific problems do you have with designing Avalon MM hw accelerators? Avalon interfacing is very simple. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20256)</div> [/b]  --- Quote End ---   Yes, First i&#39;m working with QuartusII 5.0 (SOPC builder) And for my specifc problems : For example my hardware accelerator needs a data as entry much longer than 32 bits so can i do? especially when the data needs to be available at a specific clock cycle. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20261)</div> [/b]  --- Quote End ---    The only solution is to have multiple 32 bits registers and writes. The bus is only 32 bits wide. What kind of accelerator are you working on? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20267)</div> [/b]  --- Quote End ---    My acelerators are: -Multiply Matrix (4,4)x(4,4) each element of the matrix take 8 bit so up to 32 bits entry http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif   -Scalar product(x1*x2+y1*y2+z1*z2)   -vectoriel Product which takes 2 Vectors V1(x1,y1,z1) V2(x2,y2,z2)   -Transformation from 2D to 3D coordinates

[Altera_Forum]

So where are you Jeroen? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif  

Nothing to Say!!! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

[Altera_Forum]

Try making your component dynamic instead of native. Dynamic components (typically memory) use byte enables so you shouldn&#39;t run into any width restrictions there. 

 Better yet, you are probably working a buffer of data so if that&#39;s the case here&#39;s how I&#39;d approach this:  1) Stuff the data into wide on-chip memory buffers 2) Feed your accelerators with data using DMA engines from the on-chip memory buffers  Step two can be done two different ways, you can use a separate DMA engine (available in SOPC Builder) or just build one on the front end of your hardware accelerator. To learn more read the component editor and Avalon memory mapped specification.

[Altera_Forum]

Hi guys. 

I&#39;m a beginner with Nios II and Quartus II. My developing board mounts a Cyclone II FPGA EP2C35. I must interface an external Camera (C3088 made of Omnivision OV6620 sensor) with that board but, i don&#39;t know how to do that. I mean, the connection to PROTO1/PROT2, it&#39;s ok, but how create the interface with the internal system?Should i use Avalon MM? I have look to Portable Reference Board project but is really hard to understand. I hope someone coul help me and give some clear advices Many thanks Paolo

[Altera_Forum]

--- Quote Start ---  originally posted by tonnoplast@Jan 10 2007, 03:42 AM hi guys. i&#39;m a beginner with nios ii and quartus ii. my developing board mounts a cyclone ii fpga ep2c35. i must interface an external camera (c3088 made of omnivision ov6620 sensor) with that board but, i don&#39;t know how to do that. i mean, the connection to proto1/prot2, it&#39;s ok, but how create the interface with the internal system?should i use avalon mm? i have  look to portable reference board project but is really hard to understand. i hope someone coul help me and give some clear advices many thanks paolo <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20469)  --- quote end ---    --- Quote End ---    Avalon-MM should be fine for what you are doing. I would read these documents to learn more:  http://www.altera.com/literature/manual/mnl_avalon_spec.pdf (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf) http://www.altera.com/literature/hb/qts/qts_qii54005.pdf (http://www.altera.com/literature/hb/qts/qts_qii54005.pdf) http://www.altera.com/literature/hb/qts/qts_qii54007.pdf (http://www.altera.com/literature/hb/qts/qts_qii54007.pdf)  (I took those links from this page: http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp) (http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp))  Avalon-MM gives you standard interface to conform to so as long as you can make your camera logic in the FPGA meet the specification, then you just feed your HDL through component editor and drop the result into your system. The most basic and common interfaces will have these signals:  writedata (data out to your component) write (write enable) chipselect readdata (data in from your component) read (read enable, sometimes your logic won&#39;t need it) address (if you have multiple locations to access in your component) clk reset

[Altera_Forum]

Thank you badomen. I will have a look again to that documentations. 

Another question. Do you think that is possible to catch datas from camera using PIO PORT with IRQ? I mean, read that port everytime a signal(PXCLK) shows a ready pixel byte, and then put that pixel on array. Thank you

[Altera_Forum]

--- Quote Start ---  originally posted by tonnoplast@Jan 12 2007, 03:37 AM thank you badomen. i will have a look again to that documentations. another question. do you think that is possible to catch datas from camera using pio port with irq? i mean, read that port everytime a signal(pxclk) shows a ready pixel byte, and then put that pixel on array. thank you <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20528)  --- quote end ---    --- Quote End ---     The interface doesn&#39;t look like it would support a PIO interface very well. I did a quick search and it looks like you are fed YUV using a clock source from the camera which comes back as back to back data.  I recommend creating a component that takes the data from the camera, stuffs the data into a memory based FIFO, then having an interrupt fire when the FIFO reaches a certain length like half full for example. Then you can have a DMA pull the data out of your component. There could be better methods depending on your system architecture so I would explorer all possibilities before diving into the design.  System Interconnect Fabric Custom Logic DMA <--- Your custom component (FIFO) <---- Camera

[Altera_Forum]

Thank you again. Just because today is Friday i hope you could answer my next question before week end. 

As me,you probably had a look to Portable Reference Platform Project in a NiosII forum section. There,it is used a Camera block and a DMA for Camera.Well, both are descripted in vhdl language,but DMA vhdl&#39;s it&#39;s understandable for me.If you could,say me what do you think of that Anyway this is my question.I&#39;d like to know if you are agree with me:  1) I must describe my camera in vhdl(structural and functional) for having it available on SOPC builder.Then in Quartus i will do the connection in order to where is placed my camera;  2)Could i use the DMA already present in SOPC for camera data flows?If not,dma vhdl description it&#39;s the only way?  Thank you  Paolo

[Altera_Forum]

Sorry...in the post before..the VHDL of DMA it&#39;s NOT understandable for me. 

And last thing..i&#39;ve tried to use PIO as i said you. I can&#39;t catch the Pixel clock signal that it&#39;s the fastest and i can&#39;t catch data.So probably PIOs are ko. Bye Paolo

[Altera_Forum]

Yes, you can create your interface component in VHDL and use it in your SOPC Builder system. The main purpose of that component is to bridge your camera interface signals to the system interconnect fabric. You would still have to connect the camera signals in Quartus via pin assignments. 

 You shouldn&#39;t have to understand the VHDL that the DMA is written in since the component is completed for you.  PIOs are simply memory mapped registers so that&#39;s why you couldn&#39;t use them for your interface. I recommend that you stuff the data from your camera interface into a small FIFO then map the read side of the FIFO to the system interconnect fabric. If you search the forum I think you&#39;ll find something similar to this in the IP section.

[Altera_Forum]

Ok BadOmen.I&#39;ll follow your suggest. 

You are really kind...and your Charlie Brown picture really relax "People NiosII shocked" like me http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif  See ya!  http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/laugh.gif