Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

JTAG UART Gotcha...

Altera_Forum
Honored Contributor II
1,696 Views

I've just been bitten by the JTAG UART hanging my system when the USB cable was disconnected.  

 

I'd read about the dangers of the 'small' mode, and I have a valid system clock timer, etc.. 

 

But, it turns out my problem was the order of the JTAG UART vs. SYS_CLK_TIMER in SOPC builder - the UART was trying to initialise before the clock, so it's call to alt_alarm_start was failing silently, and the timeout procedure never gets called... 

 

Easy to fix, but a pain to track down... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif  

 

- Roddy
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
629 Views

What do you mean by &#39;order&#39;. I thought device init order was canned - so how did you fix it?

0 Kudos
Altera_Forum
Honored Contributor II
629 Views

Devices are initialised in the order they appear in SOPC builder, so you use the &#39;move up/move down&#39; buttons to place the clock above the JTAG UART. alt_sys_init.c will then get rebuilt to reflect this new ordering. 

 

- Roddy
0 Kudos
Reply