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SDRAM byte (8-bit) write access

Altera_Forum
Honored Contributor II
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Hi all, 

 

I've a NiosII system based on EP1C6144, with an extrernal 2Mb 16-bit wide SDRAM.  

 

While writing SDRAM with 16 or 32-bit wide data gives the expected result, if I try to write a single byte (8-bit) I find 2 adiacent bytes written in SDRAM with the same value. 

 

To check this behaviour I wrote a simple in-line assembler that make me sure I have not compiling problems: 

 

  __asm__  ("nop \n\t"                    "movi r6, 0x12 \n\t");                         // Loads data to be written (0x12) in register R6                 __asm__  ("movhi r7, %hi(0x1F7F84) \n\t"                    "ori r7, r7, %lo(0x1F7F84) \n\t");       // Loads address data has to be written to (0x1F7F84) in register R7   __asm__  ("stb r6, 0(r7) \n\t");                           // Writes BYTE in R6 in address pointed by R7+0   

 

Before these instructions I have the memory window displaying 

 

 0x001F7F84    0x00 0x00 0x.... 

 

and after instructions... 

 

 0x001F7F84    0x12 0x12 0x.... 

 

I checked all SDRAM's timing parameters and they seems to be right, in effect code runs from SDRAM and 16 and 32-bit accesses are correct, and also any read access. 

 

Any idea? 

 

Thanks all, 

 

Paolo
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Altera_Forum
Honored Contributor II
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The one thing which occurs to me is that your code won't work on processors with a cache. You need to use the STBIO instruction instead. 

 

And you should probably use builtin_stbio instead of using inline assembler because the compiler can optimise it much better (or use the HAL macro IOWR_NATIVE8 or something like that which does the same thing). 

 

I assume you've checked your objdump file to make sure the compiler hasn't split up your assembler statements (which is will sometimes do to make optimisation better).
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Altera_Forum
Honored Contributor II
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The processor I use is the "e" version, without any cache... 

 

However I'll try to follow all your suggestions, but I think is an hw problem: I just noticed that UDQM & LDQM signals are wired together to Nios' DQM0...  

 

This bring me to think that byte access is not possible on my board... 

 

Thank, 

 

Paolo
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