Managing in software new SOPC Builder component

Altera_Forum · ‎01-19-2006

I work with Stratix. I've developed a new component in SOPC Builder.

I connected it to avalon slave. There are a couple of signals, which i assigned as global_signals.So there are 4 avalon_bus signals as following: READ_DATA, READ, IRQ and CLK (clock-to read the data stream while READ is assigned to 1, more exactely it clockes fifo chanel inside my component and READ enables fifo to be read).

Now I need to read the data at the software level. I do it with command:

p=(int *)CAM_INTERFACE_0_BASE;

a=*p;

// cam_interface_0 is my component name

the same result gives instruction:

iord(cam_interface_0_base, 0);

instantation in sopc shows 4bits mapping, that means base address: 0x01010820 and end address 0x01010823, do they show 16bits of read_data register? then what about irq and read registers? where they exist?

i don't know when can i read it, cause i don't know how to determinate if there is irq request from my ip, i don't know neither how to force read to be asserted.

i've checked through documentation, i see, there is ienable register, 'ctl3' in register file. how can i access it? can i try with nios2.h - nios2_read_ienable(..sth??..).

the 2nd problem is that when i read with for loop

for(i=0;i<a;i++)

{

a=IORD(CAM_INTERFACE_0_BASE, 0)

}

then every 2 data I read only 1. I verified this with signal tap. As I said before it is read from fifo. How can I menage this.

If you can recomend just some documentation or a piece of example codes i'll be really thankfull.