Question about Data Cache and the compiler

[Altera_Forum]

Hi, 

 I have the following situation in a Nios2 design: - the Nios executes some code - then the Nios stores all registers (also the control registers) onto the stack - the Nios is reset - when the Nios restarts the software execution, the instruction and data cache is initialized (as in the original crt0.S), but then the registers are restored form the stack and the program counter is set to the address after the code, where the registers were saved - so the Nios continues the software execution if nothing happend.  In a Nios2 design with off-chip SRAM (that is not reset or cleared), this seems to work fine. After reset, all necessary registers are restored. To do this, I modified the crt0.S.  Ok, the problem is that this idea does not work in a Nios2 design with a Nios2-f (the biggest version), the small and the medium Nios are ok. I tried to isolate the problem and found out, that the data cache is the problem. The Nios2-f without any data cache works fine, but with dcache, resuming the program execution crashes the Nios.  After putting all registers onto the stack, I tried to flush both caches and added a 'sync', but it does not help. I am not sure if I am right, but my idea is that the problem results from the fact, that the software must decide to use or not to use the data cache. So I write my normal code and the compiler decides which data is cached and which is not cached (using the stw/stwio/ldw/ldwio commands). I think because of this, I cannot jump to the address where to resume the execution. After the reset, the data cache is cleared, there is nothing in it. But the software code at the address where to resume might expect some values in the data cache, since the compiler cannot know that the Nios is reset at this point and that the execution might be resumed by the way described above. For me, this is the reason why resuming the execution with the Nios2-f with data cache does not work. (I hope you could follow my weird thoughts up to here.)  Is there anything I can do to tell the compiler that the data cache was cleared somewhere in the program? I tried to use initd instruction after storing the registers onto the stack and before resetting the Nios. My idea was, that the compiler recognizes that the data cache is cleared and so avoids using the cache at this point. But it did not help. Any ideas what I can do to solve this problem? Is there perhaps a way to read out the data cache and write it direclty (to put the data cache also onto the stack and restore it like the registers)?  I hope it is not to difficult to get the point of my problem. If it is absolutely not clear, tell me and I try to explain it again ;-)  Thanks to everyone who can help me solving this problem.  Bye  Bernd

[Altera_Forum]

Hi Bernd, 

 try to understand the datacache by reading chapter 7 of the following manual  \altera\kits\nios2\documents\n2sw_nii5v2.pdf  It tells you about bit 31 and datacache... I beleive that (but I'm not sure) only the -f version could have this sort of problem...  Good luck. Cheers,  Danny

[Altera_Forum]

Hi Bernd, 

 First, do what Danny suggests: read the manual.  Then review: http://forum.niosforum.com/forum/index.php?showtopic=3190 (http://forum.niosforum.com/forum/index.php?showtopic=3190)  Then the following will be more useful:  > I tried to use initd instruction after storing the registers onto the stack and > before resetting the Nios  Use flushd to flush the entire data cache. Look at alt_dcache_flush_all() ... but do pay attention to the bug fix by James in the topic above.  Or from u-boot:    /* flush_dcache (unsigned char *p, int len)     *     * To flush entire cache:     *        flush_dcache ((unsigned char *)0L, DCACHE_SIZE)     */    .text    .global flush_dcache flush_dcache:    add    r5, r5, r4    movhi    r8, %hi(CFG_DCACHELINE_SIZE)    ori    r8, r8, %lo(CFG_DCACHELINE_SIZE) 0:    flushd    0(r4)    add    r4, r4, r8    bltu    r4, r5, 0b    ret  Regards, --Scott

[Altera_Forum]

Hi Danny, hi Scott, 

 thanks for your answers. I did what you suggested and read the according manual part very carefully again. While reading the chapter, I became aware of my mistake. I trashed some values because I saved the register values to the stack bypassing the cache. After (!) that, I flushed the cache... I fixed this error, tested it, and what should I say, it seems to work! Thanks a lot.  Bye  Bernd