Multiple Clocks to on board compoents

[Altera_Forum]

I am working on a design (on the Stratix Professional Board) that utilizes the on-board SDRAM and the Lancelot VGA DAC I attached on. Currently, the design is configured at 50Mhz. The SDRAM (U57) must be at the same frequency as the core, so I drive it using a pll.  

 I need the SDRAM at the core frequency of 50Mhz, but since I want 640x480 resolution by the DAC, I have to get a 25Mhz clk signal to the DAC. However, since the DAC and the SDRAM use the same clock buffer (U2, ie. PIN_E15), this is impossible to do. The problem is that it seems I can only distribute a single clock to various parts of the board.   The only solution I see right now is to lower the core frequency to 25Mhz, to match the required frequency of DAC for generating 640x480 resolution. But this is such a poor workaround. Any ideas on this issue?  -Mark

[Altera_Forum]

You should to change video_clk into pll to 25 MHz, but not clk of DAC.

[Altera_Forum]

--- Quote Start ---  originally posted by camelot@Feb 5 2005, 06:25 AM you should to change video_clk into pll to 25 mhz, but not clk of dac.  --- Quote End ---   It needs change both the vdeio_clk to 25.175Mhz and the PCB design of Lancelot board.  In the Lancelot board, you must cut-off 1-2 connection of J1, connect 2-3 of J1,   and add a 25.175Mhz OSC to X1.  Of couse the related registers of Lancelot board must be also changed to match 640*480   mode.  Now, because the clk for video DAC is from 25.175MHz OSC of Lancelot board, not from   buffered clk from PIN_E15, you can maintain the PIN_E15 to 50 MHz to SDRAM devices and   CPU.  Hope this is helpful.  -- Kaku

[Altera_Forum]

--- Quote Start ---  originally posted by kaku817+feb 17 2005, 03:15 am--><div class='quotetop'>quote (kaku817 @ feb 17 2005, 03:15 am)</div>  --- quote start ---  <!--quotebegin-camelot@Feb 5 2005, 06:25 AM  you should to change video_clk into pll to 25 mhz, but not clk of dac.  --- Quote End ---   It needs change both the vdeio_clk to 25.175Mhz and the PCB design of Lancelot board.  In the Lancelot board, you must cut-off 1-2 connection of J1, connect 2-3 of J1,   and add a 25.175Mhz OSC to X1.  Of couse the related registers of Lancelot board must be also changed to match 640*480   mode.  Now, because the clk for video DAC is from 25.175MHz OSC of Lancelot board, not from   buffered clk from PIN_E15, you can maintain the PIN_E15 to 50 MHz to SDRAM devices and   CPU.  Hope this is helpful.  -- Kaku [/b]  --- Quote End ---   Sorry, I am wrong... Camelot is right.  No additional H/W modification is needed!  It needs only change &#39;vga_clk&#39; to 25MHz and maintains PLD_CLKOUT (PIN_E15) in 50MHz.  Of couse the related registers of Lancelot board must be also changed to match 640*480   mode.  -- Kaku