Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

NIOS FPU Performance

Altera_Forum
Honored Contributor II
1,803 Views

Hello everybody: 

 

I've been testing the NIOS II FPU performance and it seems to be very bad unless I'm missunderstoding something. When running the tutorial example I get the following results: 

 

Addition: Time(Clocks) No FPU approximately 254 cycles 

With FPU approximately 22 cycles 

 

Similar results for sub and multiply instructions. 

 

In my opinion 22 cycles is too much for an FPU. I've been searching the web and there are other processor with the FPU integrated within the pipeline which perform operations in only 1 cycle (plus latency).  

 

Is the NIOS II FPU integrated within the pipeline?  

How many cycles does it itakes to perform an operation? 

The information provide by Altera doesn't talk too much about this issues. 

 

Thanks in advance, 

Luis
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
796 Views

 

--- Quote Start ---  

originally posted by luisalba@Feb 1 2007, 05:20 AM 

hello everybody: 

 

  i've been testing the nios ii fpu performance and it seems to be very bad unless i'm missunderstoding something. when running the tutorial example i get the following results: 

 

addition:  time(clocks)  no fpu approximately 254 cycles 

                                    with fpu approximately 22 cycles 

 

similar results for sub and multiply instructions. 

 

in my opinion 22 cycles is too much for an fpu. i've been searching the web and there are other processor with the fpu integrated within the pipeline which perform operations in only 1 cycle (plus latency).  

 

is the nios ii fpu integrated within the pipeline?  

how many cycles does it itakes to perform an operation? 

the information provide by altera doesn't talk too much about this issues. 

 

thanks in advance, 

luis 

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=21109) 

--- quote end ---  

 

--- Quote End ---  

 

You may have a look at www.opencores.org. There is a good FPU project. This implementation is pipelined. 

According to the doc: 

 

- Nr. of logic elements : 

*3468 

 

- fmax: 

100 MHz 

 

-Clock Cycles: 

Addition/Subtraction 

 

Multiplication 

12 

 

Division 

35 

 

Square-root 

35 

 

Hope this helps. 

BR
0 Kudos
Altera_Forum
Honored Contributor II
796 Views

The Nios II FPU has the following calculation times (Taken from the Nios II 6.1 release notes): 

 

* 6 cycles 

+ and - 8 cycles 

/ 32 cycles 

 

I suspect you have overhead being accumulated in the time measurement.
0 Kudos
Reply