NIOS GPIO and Metastability question

Nios® V/II Embedded Design Suite (EDS)

Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++

NIOS GPIO and Metastability question

1,011 Views

Hi everyone!

Just a simple confirmation.

We had implemented an NIOS project with some GPIOs (the ones provided in QSYS)

The interfaces are asynchronous respect to the internal clock domain.

I assume initially that the input IPs for the NIOS had a double flipflop but looking at the RTL netlist I notice that there is combinatorial logic already at the input or after the first flip flop. :-/

So the NIOS GPIO is done basically for syncronous interfaces with the NIOS Clock and i case of asyncronous it is expect that the desinger manage the resampling for metastability outside?

Is my assumption correct?

thanks in advance

Ale

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.