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Hi team,
we are upgrading the design from 13.1 to 22.1. In our design we have ethernet ip TSE, in 13.1 ethernet TSE is handled SGDMA while we generate the bsp the SGDMA files are generated, and application built without any issues. But in Quartus version 22.1 the same design is migrated and generated .sopcinfo file, while generating bsp the SGDMA files are missing whereas the mSGDMA files are generated. we are facing issues no SGDMA files are available.
Board we are using is Cyclone 5 - 5CGTFD9D5F27C7.
can you please give some information on this issue.
Thanks in advance.
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Hi
The example for the Nios@ with SGDMA have been release a long time ago and there is no longer support for the example design.
I managed to find a more recent example design for the Nios2 with mSGMA for the quartus 18.1 and managed to upgrade it to the 22.1 version.
Could you try the example below:
https://community.intel.com/t5/FPGA-Wiki/MSGDMA-design-example/ta-p/735335
Regards
Jingyang, Teh
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