NIOSII error when updating to Quartus II v5.1

Altera_Forum · ‎11-28-2005

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif

Hi,

I have a CycloneII DSP kit. It has a few NiosII samples designed for

QuartusII v5.0.

I just update QuartusII to v5.1. However, in SOPC, it shows an error:

"cpu: Address range of instruction master crosses a 256-MByte boundary.

Not supported by NiosII tool chain".

The address for DDR2 defined in the example is; 0x4000000 to 0x7FFFFFF.

The error message will disappear after deleting DDR2 component.

Openning the same project in SOPC in QuartusII v5.0 does not show the

same error.

Would you please help me understand why?

Thanks very much!

Kevin

Altera_Forum · ‎11-29-2005

There is a restriction of 256MB on Nios II instruction master is due to the jumping distance (the jump instructions can jump up to an addresses 26 bits away so 2^26 * 4(bytes/word) = 256MB)

It's been a while but I could have sworn we used one quarter of the address range of the DDR2 on that board so that the range was small enough. Could you let me know via email which design you have seen this issue with (name of the design). Also did you modify this design in any way (if so what did you change?). Judging by the address range you are seeing some addressing settings were wiped out (we reduced the number of DDR rows to reduce the address range by a factor of 4 if I remember correctly)

I hope in some way that explains what you are seeing.

Altera_Forum · ‎11-29-2005

Hi, Badomen,

I have sent the information through email. If you need more

details, please let me know.

Thanks!

Altera_Forum · ‎11-29-2005

Kevin,

The Nios II examples, for the Cyclone II DSP boards, are all based on using only 64MB of the available 256MB. Nios II's implementation of GCC includes a CALL instruction with a destination address that can span no more than 256MB. SOPC Builder flags this as an error (or warning) because the GCC toolchain could break.

Your best bet, to get up and running on 5.1 in a timely fashion, is to place the PTF, QPF, and QSF, for the project that you're interested in building, in a new directory, re-generate your SOPC Builder system and re-compile in Quartus II....

Additionally, you may have to remove and add the DDR2 component into the system, using the latest DDR/DDR2 core (has to be supported by QII 5.1!). The DDR2 MegaWizard's default, of 256MB, for this DIMM, will not work in an SOPC Builder system. You need to change this default to 64MB.

Best of luck!

- slacker

P.S.: If you just want to attempt to run some software, on an existing 5.0 design, you should be able to:

1. Program the FPGA using one of the included project's SOFs.

2. Open the Nios II IDE up, directly.

3. Follow the rest of the instructions, with the caveat that you'll have to add the path(s) to the HW project's PTF, manually.

EDIT FOLLOWS:

NOTE: Only the Nios II instruction master has this 256MB limitation. The data master can be connected to anything up to 2GB address span. If you want to get going, you can keep the default 256MB address span, but only connect the DDR2 to the Nios II's data master.

Altera_Forum · ‎11-30-2005

Thanks!