NIOSII simulation

[Timothy_Adegbite]

Hello,
Please, I am interested in the NIOS II application.
I am looking at:
1. Creating a NIOS II processor on the intel platform designer(Qsys).
2. Writing an embedded code for it on eclipse.
3. Writing a VHDL code that exchanges data with the NIOS II.
4. Simulating the whole data exchange between the NIOS II processor, Eclipse and VHDL all on modelsim.

Please, can anyone help with the best approach to achieve the above ?

Thank you.

[Timothy_Adegbite]

Please, can anyone kindly help with my earlier post ?

[BoonBengT_Altera]

Hi @Timothy_Adegbite,

Thank you for posting in Intel community forum and hope all is well.

Just a note, unfortunately for Nios II product it has been deprecated and would advise to move NiosV instead. More details can be found in the link below:

- https://www.intel.com/content/www/us/en/content-details/781327/intel-is-discontinuing-ip-ordering-codes-listed-in-pdn2312-for-nios-ii-ip.html?DocID=781327

Hence with that if you are looking for simulation with NiosV, details steps on how to do that can be found in the following design example and would be a good starting point for the situation you mention:

- https://www.intel.com/content/www/us/en/docs/programmable/726952/24-3-1/simulating-processor-designs.html

Hope that clarify.

Best Wishes

BB

[Timothy_Adegbite]

Hello @BoonBengT_Altera ,

Thank you for your response.
I am currently exploring the link you have provided.
Please, in addition to simulating the NiosV on questa, I also want to concurrently simulate the interaction between the VHDL code on quartus and the Embedded code on Nios V, I cannot find any section in the link that explains this. 
please, can I get to do this on Questa ?

[Timothy_Adegbite]

Hello Everyone, 
Please, can anyone kindly help with answers to my question ?

[BoonBengT_Altera]

Hi @Timothy_Adegbite,

Apologies for the delay in response due to the long holidays in our site last week.

For the mention to simulate both the Nios V processor (with your C code) and your custom VHDL module in one integrated Questa simulation.

Would suggest to add the NIosV system normally in platform designer, followed by exporting the files from quartus. You can than compile the design in Questa by vsim command (Note: you may edit the msim_setup.tcl to include your VHDL file manually if it wasn't added to platform designer) and then compile the software side of things at NiosV using the elf2hex (e.g., elf2hex --input=your_app.elf --output=app.hex --base=0x0 --end=0x1FFFF)

Hope that clarify.

Best Wishes

BB

[BoonBengT_Altera]

Hi @Timothy_Adegbite,

Greetings, just checking in to see if there is any further doubts in regards to this matter.

Hope your doubts have been clarified.

Best Wishes

BB

[BoonBengT_Altera]

Hi @Timothy_Adegbite,

Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome. Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

Best Wishes

BB