Newbie

[matrixrv]

: Is for Avalon bus an Intel IP an formal equivalent with AXI Master from Xilinx ?

[KennyTan_Altera]

Avalon bus spec is different than AXI in xilinx. However, you can still make connect in btw them. The qsys will add synchronizer towards it.

[KennyTan_Altera]

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[matrixrv]

My target point is why AXI Master have no external data port.The Axi master can control read data cycle on AXI bus , write data Cycle on Axi bus , can control through its signal HOLD,HOLDA bus acces of certain slave.For any other data path - like a FTDI 8 bits data path ,it provide no connection.

Let say a 8 bits data path from FTDI RS232.we need a UART slave on AXI bus. 

Let say an another 32 bits data path an PCI bus.need an slave PCI.It mean that for any non AXI data path need a slave for that.

In Avalon architecture suppose this is the same.