Re: Nios Development kit

Altera_Forum · ‎05-24-2005

did someone ever use a nios2 dev kit statix edition with a configuration which doesn't use a nios core????

Altera_Forum · ‎05-24-2005

Yes but the design didn't do much (just putting a safe design in so that I don't damage anything I manually connected to the board). Are you asking if you need a Nios II processor in order to use the device? If so the answer is no, it's only called a Nios development board because it has a lot of peripherals that work well in an embedded system (SRAM, SDRAM, Ethernet, EPCS, Flash, Uart, Pushbuttons, LEDs, etc....) but there is nothing that forces you to have a Nios II core in the design.

Altera_Forum · ‎05-25-2005

Ok, thanks, I won't have to throw my board away!! Now I'm sure that something else than their examples can be loaded, because I wondered if it was possible!!

But I can't find why my programmed files don't stay active after loading. I think they are safe, I don't have any errors during compile and program sequences. Do tou know if there is a special pin to connect to gnd or vcc to really enable programming??

Altera_Forum · ‎05-25-2005

Ice Tiss,

See my answer to the other thread that you started asking about non-Nios designs in your dev board....

Altera_Forum · ‎05-25-2005

I did! Thanks!

I tried to change unused pin's config, but it doesn't run better. I hadn't seen this options window before. So I tried this and other options, but nothing makes a different result. I don't have any other idea.

Altera_Forum · ‎05-25-2005

Can you post the link to your other thread in here. Reading this one it sounds like something went wrong and now you are trying to determine if the board is toast. Here's a pretty good safe design, bring in the 50MHz clock input and reset, wire them to a wide counter, then take 8 bits out of the counter and wire those to the LEDs (to figure out which bits to wire, take the clock period (20ns) and crunch the numbers to find out what bits to use so that it's not too slow, or so fast you can't see them switching).

Also if this configuration doesn't seem to stay, have you been setting unused I/O to "tristate" in Quartus II? I accidentally made a design that kept toggling a bit going to the CPLD that would reset the design all the time due to the unused I/O not be driven to tri-state (maybe you have done the same).

Good-luck

Altera_Forum · ‎05-26-2005

Thanks BadOmen.

I've already did so, my problem was not to design the counter, for this I don't have problems! And now that I found "the secret pin"!!, there are no problems anymore. As I say in the other topic called "programming .sof file with nios dev kit stratix", the problem was coming from a pin, which might be used for PLD reconfiguration. For Ep1S10 device, it is the pin U2 called in examples "PLD_RECONFIGREQ_N", and this pin must be set at VCC in order it doesn't command a reconfig after the end of loading a program. I don't know if I undestood it correctly, but all I know is that now, it works fine with this. I had tried setting unused pins to tristate, but I didn't get a better result than before. I find strange it works for you and not for me! There may be some black magic in the air!!

Thanks for your help