Nios II Flash Programmer with 8-bit CFI Interface

[Altera_Forum]

Hi All, 

 I have 8-bit CFI Flash interface on my board.   I got error ..   # Programming flash with the datafile "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x02800000 "test.flash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK   : Checksumming existing contents   Checksums took 0.0s  Erase not required  00000000 ( 0%): Programming   Program failed at offset E  Leaving target processor paused   Is there any solutions ?  Regards, Hardik Sheth

[Altera_Forum]

this could be due to several reasons. 

but we would need more informations about your design. how did you setup the cfi flash inside sopcs ? how is your external cfi flash connected to the fpga, especialy the adr bus.  yould you post some files of your project ? the sopcinfo file and the toplevel file that has the interface between the sopc design, which holds your cfi flash controller (via tristatebridge), and the external pins.

[Altera_Forum]

I have attached screen shot of my sopc and quartus system. Flash and FPGA data interface is 8-bit.  

 CFI Flash is M29W640FB.

[Altera_Forum]

your toplevel connectivity shows that sdram and cfi share some signals like adr ... is that correct ? 

also your signal tri_bridge_byteenablen has goes to sdr_be is that correct ? the name ...byteenablen has a "n" at the end, might indicate negative logic.

[Altera_Forum]

I am having a similar problem. I have a system with: 

 UART (RS-232) + NIOS + ON-CHIP RAM, C program runs OK UART (RS-232) + NIOS + ON-CHIP RAM + DDR, get "leaving processor paused" problem.  It does appear like a timing-related issue but I cannot find a proper .sdc generated by SOPC builder for the first case to improve on. What I see in the first case is that the clock frequency is set to 1 GHz as all clocks are (as if proper clock constraints are missing) through I set in SOPC builder the frequency of the input clock to the system to 144 MHz.  The first case appears to work because it is a simple system.  The second case with DDR appears to fail because the NIOS is now constrained differently.  cpu.sdc does not contain any clock frequencies.  I am using Quartus II 8.0 and NIOS 8.0 on Linux with OpenCore Plus evaluation mode.  Any information would be appreciated.  RAUL

[Altera_Forum]

--- Quote Start ---  Hi All,   I have 8-bit CFI Flash interface on my board.    I got error ..     # Programming flash with the datafile "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x02800000 "test.flash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK   : Checksumming existing contents    Checksums took 0.0s  Erase not required   00000000 ( 0%): Programming    Program failed at offset E  Leaving target processor paused     Is there any solutions ?   Regards, Hardik Sheth  --- Quote End ---       I had a similar problem and had to delay the control signals (to the FLASH) before they left the FPGA. I used a DFF and delayed the signals: read_n, write_n and select_n by one clock cycle. I found that the address lines were not stable by the time the control signals went active - that is why I delay them. I let them do inactive asynchronously by connecting the 'D' input of the flip flop to the 'preset' input through an inverter (not gate).

[Altera_Forum]

--- Quote Start ---  I am having a similar problem. I have a system with:   UART (RS-232) + NIOS + ON-CHIP RAM, C program runs OK UART (RS-232) + NIOS + ON-CHIP RAM + DDR, get "leaving processor paused" problem.   It does appear like a timing-related issue but I cannot find a proper .sdc generated by SOPC builder for the first case to improve on. What I see in the first case is that the clock frequency is set to 1 GHz as all clocks are (as if proper clock constraints are missing) through I set in SOPC builder the frequency of the input clock to the system to 144 MHz.   The first case appears to work because it is a simple system.   The second case with DDR appears to fail because the NIOS is now constrained differently.   cpu.sdc does not contain any clock frequencies.   I am using Quartus II 8.0 and NIOS 8.0 on Linux with OpenCore Plus evaluation mode.   Any information would be appreciated.   RAUL  --- Quote End ---     Found out that the problem was a hanging NIOS reset_n pin. Once NIOS is properly reset the processor can be downloaded reliably.

[Altera_Forum]

good tip Praul - I will look at creating a reset first and look at its stability.