Nios® V/II Embedded Design Suite (EDS)
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Nios Vs. Nios II

Honored Contributor II

I've not recevied the update yet (impatient!), so I'm reading the manuals from the altera's website.  


I'm hoping that branch delay slots are a thing of the past, the branch instructions don't seem to mention them like they did in the old manuals. Can anybody confirm this. 


And seeming as a few of the nios development guys read/post here, can they explain why they existed in the nios architecture in the first place (cough *mistake*)? 


Anyway, impatiently waiting for the Nios II update to arrive. 


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Honored Contributor II

Hi Adrian, 


Yes, the branch delay slots are gone! I used to maintain the Nios core and the nios-elf-gcc compiler, and then I created the Nios II instruction set. 


I didn't design the first few Nios implementations, but I can say that the Nios branch delay slots just fell out from the original Nios pipeline (as they did in the early Berkeley RISC and Stanford MIPS pipelined RISC processors). But then as we added pipeline stages to Nios for performance, we needed to make the new Nios pipeline pretend that it was a shorter pipeline for code compatibility. The branch delay slot no longer was serving its intended purpose as a simple substitute for branch prediction. 


You'll also find that the Nios prefix instruction is gone. There are nice software reasons for such an instruction, but it is a big source of complexity. And complex control logic hurts performance in an FPGA implementation. 


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