Nios not running (newbie)

[Altera_Forum]

Nios does not appear to be running at power-on. I say this because I get nothing from nios2-terminal when executing while(1) { alt_putchar('A')};. I have a Nios Processor, JTAG UART, onchip_memory, and a simple custom peripheral (holds registers that I can read/write from Nios). 

 I can read and write (using System-console) to my custom peripheral and it appears to work: (Note the following: set niosii_proc [lindex [get_service_paths processor] 0]) % master_read_32 $niosii_proc 0x40000 1  0x0000000F   % master_write_32 $niosii_proc 0x40000 0x2    % master_read_32 $niosii_proc 0x40000 1  0x00000002   Also, my JTAG UART is at 0x4000. When I execute the following in system-console, a character outputs to the nios2-terminal:   % master_write_32 $niosii_proc 0x4000 0x51   And, when I read from 0x00000000 and read the first 8 words, it looks just like the first 8 words in the onchip_memory hex file. So it appears that the code is loaded properly.    When I run "processor_get_register $niosii_proc pc", I get 0x00000000 (Is this a good value when the processor is stopped as in "processor_stop $niosii_proc" ? if so, the program counter is pointing to the correct address. Also, when I look at other registers ("processor_get_register $niosii_proc r4", etc) I get oxdeadbeef. Is this normal when the processor is stopped (I would think not as this would render debugging rather useless)?  So, I know my custom peripheral is working fine since I can read/write registers. The reset is active low to the FPGA. So the FPGA appears not to be in reset, and has a clock. Note that the board I am working on is known-good. The pin file which provides a check of my constraints looks correct (in other words, Quartus correctly read and used my pin placement constraints). I am using Quartus and SOPC builder 10.0 to generate the system.  I simulated the system using the automatically generated sim files provided from SOPC builder. I even used the generated script in modelsim. The processor seems to work just fine in sim. Note that the above while(1) loop menioned above has a few other statements that copy registers in addition to the putchar statement. I see these registers being read/written to from Nios.   Questions I couldn't answer: Does the Nios take an active low reset? Or is it's reset active high? Looking at the SOPC generated top level VHD file, I see *reset_n everywhere which would indicate to me that Altera uses active low resets.    How can I tell if the processor is being held in reset?   Thanks for reading this!

[Altera_Forum]

UPDATE: 

 OK, I decided to start from scratch. Nios CPU + onchip_memory + JTAG UART + PIO. Simple system.   I loaded up the EDS, with the Hello World Small project.    Compiled / P&R, and then programmed the FPGA. The system works. So it looks like I have some issue in my original system. I'm going to add my peripheral onto this new system, recompile, and then see if everything still works....

[Altera_Forum]

I built the system back up, as I originally had it except that the address space was mapped a little differently. I don't see how this could have caused the original problem since there were no overlapping address areas among peripherals (I don't think SOPC builder would even generate a system that was mis-configured).  

 But, my system is working.