Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
12748 Discussions

Nios2 Flash Problem

Altera_Forum
Honored Contributor II
‎11-30-2006 05:32 AM
1,031 Views

I use the SST39VF320 flash on my custom board with a EP2C35F672C8, it's a 4M bytes and 16 bits flash and supports CFI.  

In the sopc buider, I chose the cfi flash ,and set the address width to 21, data width to 16. the size show below is 4M bytes. 

After the generation, I found the address width is 22 in the quartus project.So I shift the bus by one , A1 from the fpga to the A0 on the flash side.Is that right? 

However, the flash doesn't work.I can't open flash in the software using the api nor program in the flash programer.It seems nios got the wrong basic information about the flash in the system init time,because console shows that the erase region is just half of the size of th flash during the program. 

My software version is both 5.1, is there any one know how to fix the problem?
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.