NiosII booting from on-chip memory SPI issue

[reubengoh]

Hi all,

I am using quartus prime 19.1 lite, and I am trying to load a simple SPI program that sends SPI commands using NIOS II processor. The board that I am using is DECA Max10 Development Board. I am able to send "$HELLOABC*" continuously when I load the program in NIOS II SDK debug mode.

The problem comes when I try to generate the .hex file using "mem_init_generate" and compile the project in quartus to generate the .pof file. The .pof file that I loaded inside my FPGA is unable to send the "$HELLOABC*" continously. It only sends 2 "$HELLOABC*" and stops abruptly (as attached in spi_output.PNG )

I have tried to load a simple led and switch program that basically turns on and off an LED, and I am able to burn it into the FPGA. So I am assuming that my steps to load the .pof file containing the NIOS II application code is correct. 

Hence, if anyone can enlighten me about why is this happening to my SPI program? 

Below attached is the hardware of my SPI program, Nios II Application Code and spi_output image from a external logic analyzer.

I am using the test code given by Altera SPI Core in the link below. 

https://www.intel.com/content/www/us/en/docs/programmable/683130/23-4/example-test-code.html

While editing it to include a while loop to send the data continuously. I have excluded the ISR to avoid any other issues. 

Thanks in Advance,

Reuben Goh

[wwanalim_intel]

Hi,

Greetings and welcome to Intel's forum.

Please give me some time to check on this issue and will get back to you with the update.

Thank you.

Regards,

Fathulnaim

[wwanalim_intel]

Hi,

I will require additional time to thoroughly investigate and delve into this matter.

[reubengoh]

Hi Fathulnaim,

Sure. Thank you for your prompt response. I will await your investigation.

Any questions please let me know.

Regards,

Reuben Goh

[wwanalim_intel]

Hi,

It appears that the ELF file is functioning correctly, but there is an issue with the HEX file. We suspect the error might be due to one of the following:

• The file being stored in the wrong RAM location.

• Incorrect arguments passed to Elf2hex.

• Function user mem_init generated wrong HEX file.

Software abnormalities due to ELF2HEX are rare, and any references are scarce.

The best approach is to review the PD address map, and the elf2hex command ran by mem_init_generate.

Both the HEX file created from mem_init_generate and download as ELF in Nios II SBT are the same.

Alternatively, we can read the OCRAM using Nios II SBT Memory Browser after download as ELF in Nios II SBT. And compare it with the HEX file from mem_init_generate.

[reubengoh]

Hi,

Thanks for your reply. Upon some digging into the memory browser, I have found that the onchip_memory2_0.hex always starts with 20000000? Why is that so? 

I have attached some images of the mem_init_generate console window and nios sbt memory browser, as well as the hex file generated by mem_init_generate and the OCRAM memory exported from nios sbt memory browser.

Regards,

Reuben Goh

[wwanalim_intel]

Hi,

Thank you for the information and file given. I will require a bit of time to investigate into it then reply back to you.

[wwanalim_intel]

Hi,

The start address on onchip_memory2_0.hex is based on the start address in Platform Designer system.

If it starts with 2000_0000, then it is mostly likely the OCRAM in Platform Designer starts from 0x2000_0000.

[reubengoh]

I see, noted. Thanks!

[wwanalim_intel]

Hi,

Can I have the QSYS project file? I want to recompile the project and recapture any warning. Mem_init failures will not return as Errors, but warnings. So, it might go undetected sometimes

[reubengoh]

Hi, 

Attached is the project folder. Thanks for your time.

Regards,

Reuben Goh

[reubengoh]

Hi,

I've got a question relating to this document below as well. 

https://www.intel.com/content/www/us/en/docs/programmable/683689/current/processor-application-executes-in-place-60969.html

When booting NIOS II from on-chip memory (RAM), why does the hardware design (attached below) indicate in this document to include the on-chip flash IP. 

Anyway I tried to use this hardware design as well in the document, but still had the same issue with my SPI. 

Regards,

Reuben Goh

[wwanalim_intel]

Hi,

For the question, On-Chip Flash IP is not necessary. It is needed, only when booting from UFM.

Thank you for the project file provided. Will look into that and find the cause.

[wwanalim_intel]

Hi,

During the generation of HDL on platform designer, did you also got "Generated completed with errors"?

Currently trying with other version of Quartus.

Will let you know any progress after this.

Thank you for being patient.

[reubengoh]

Hi, 

No I did not get the message "Generated completed with errors". Below attached is my generated message.

Regards,

Reuben Goh

[wwanalim_intel]

Hi,

Thank you for the reply. Please allow me some more time to investigate.

[wwanalim_intel]

Hi,

I just regenerated and recompiled the project. I tested on our side and it working. Below I will attach the folder.

[wwanalim_intel]

We recompile the design using 20.1 lite. There will be ready to test folder inside which contain pof and sof file.

[wwanalim_intel]

Hope it will be working on your side.

[reubengoh]

Hi Fathulnaim, 

Thank you for your help.

I have tried loading your .pof file using 20.1 lite. After power cycling the board, I am able to get more signals now instead of 2 "$HELLOABC*", now I am getting 53 "$HELLOABC*LF", however it still stops and is not running in a continuous while loop as I expect.

I will try to compile the file again in 20.1 lite and see whether it will work.

Regards,

Reuben Goh

[wwanalim_intel]

Hi,

Thank you Reuben. Kindly updated to us after another compilation.