NiosII continuously rebooting

[Altera_Forum]

Hi, 

 My niosII is continuously rebooting at the same code position. The Nios is running on an external SDRAM (I'm using a cyclone IV EP4CE30F484). The memory test runs OK (it looks like the memory test project size is so small that doesn't make it crash). If I add more code it reboots at a different position (so it is not related to a specific line of code - I made it crash on a printf for example). The only way I found to make it work was changing the exception vector offset (it was originally 0x000020 and I changed to 0x20020). When changing the offset I did run the memory test again on the positions where the nios was running originally and it looks fine. It fails consistently (regenerating the Qsys or recompiling made no difference, so I doubt it is a signal integrity issue). Adding more instruction cache made no difference.  An interesting thing is that it crashes at a different position when debugging.  Does anyone have any idea why it is crashing when the vector offset is set to 0x000020?  *TimeQuest timing analysis looks perfect.  Many thanks for your help

[Altera_Forum]

what is your nios boot option? there should no option for boot from SD ram

[Altera_Forum]

I have a serial flash where the configuration files are. My reset vector is the flash and my exception vector is the SDRAM. 

What I've noticed is that when running it from Eclipse (with an older code version on the flash) it crashes at some point and jumps to the old software version on the flash.  Thanks

[Altera_Forum]

this threat seems is quite similar for what you are doing, not sure if you did some changed in the bsp and liker files. 

 http://www.alteraforum.com/forum/showthread.php?t=46146

[Altera_Forum]

Hi, 

 Thanks for the response. My bootloader is on the flash.  I have used this configuration for other projects and it always worked fine. And for this project it works if I add some offset to the exception vector (or run a smaller C project).

[Altera_Forum]

ops.... do you enable any watchdog timers for your usage?

[Altera_Forum]

No, I don't. 

 I tried enabling the runtime_stack_checking, exception_stack and interrupt_stack on the bsp editor but it didn't make any difference.

[Altera_Forum]

I also tried with the exception vector pointing to the on chip memory for a faster response, but it is still crashing.

[Altera_Forum]

Any other suggestion? 

 Thanks!

[Altera_Forum]

some other forum mention to have a test with the hardware via Avalon-MM Traffic Generator and BIST Engine to test the SDRAM basic functionality. probably you have did that earlier..

[Altera_Forum]

Hi, 

 I tested the SDRAM with the NIOS using the memory test template. If I'm not wrong it's going to be a similar test

[Altera_Forum]

really out of clue already...... maybe other person help to comment some

[Altera_Forum]

Are you using interrupts? If you have some code that make the CPU crash in an ISR it will appear to crash at random locations. 

If you debug it step by step does it also end up rebooting? Do you have anything connected on the reset signal in your QSys project? Could something on the hardware level trigger a reset?

[Altera_Forum]

--- Quote Start ---  Are you using interrupts? If you have some code that make the CPU crash in an ISR it will appear to crash at random locations. If you debug it step by step does it also end up rebooting? Do you have anything connected on the reset signal in your QSys project? Could something on the hardware level trigger a reset?  --- Quote End ---    He mentioned earlier no interrupt been used, quite strange issue.

[Altera_Forum]

more information: 

 There is a function that has two nested for loops that initialize a array of a struct variable. When I commented it out the code stopped crashing. When that function is there it crashes and reboots. However, if I change the exception vector offset from 0x00000020 to 0x00020020 (and with the function uncommented) it stops crashing in that function and crashes somewhere else. :confused: