Opencores PCI bridge core

[Altera_Forum]

Has someone used the Opencores PCI bridge core? What was your experience? 

 I need to build a Cardbus (32bit PCMCIA) - FPGA card using a CyclonII device.  I want to use this core to read/write to devices attached to an avalon bus,  therefore i only need a PCI target core.   Do you think that using this core is a suitable way to go?   If not - any suggestions for a different core (wchich costs less than $2000 on royalties).  Thanks for your help.   Klaus

[Altera_Forum]

Hi Klaus, 

 I've been using opencores PCI for over a year now. My application is a standard PCI form factor card, 32-bit, 33 MHz. My configuration is very similar to what you describe: target access to avalon devices, but I also tried bus mastering as well.  > Do you think that using this core is a suitable way to go?  That depends on what you mean by 'suitable'. Technically, it can be made to work -- but support is limited to the relatively quiet mailing list. So you'll have to spend some time developing your own expertise with the core.  You'll also have to pay close attention to your (avalon) bus architecture and arbitration priorities as they will affect timeouts within the core. Shared access to SDRAM for example, can be a real problem.  Regards, --Scott

[Altera_Forum]

Thanks Scott 

 No SDRAM - just SRAM and register access....  I'm planing to use some fast external SRAM and write  some code to get something like a virtual dualported ram device. I hope this eliminates collisions on the avalon bus ....

[Altera_Forum]

> like a virtual dualported ram device. 

 Yep, that's what I ended up doing & I haven't had any problems.  Keeping the dual-port memory and registers outside the system module is handy if your host-side software needs to synchronize ... by driving the system module reset ;-)  Let me know how it works out for you ... we will have our first spin PCMCIA hardware back in about a week ... but we were planning on just the 16-bit PC Card implementation.  Regards, --Scott

[Altera_Forum]

> Let me know how it works out for you ... we will have our first 

 I think this will still take a while, i am just implementing the core functionallity and the prototype hardware production will not start until i know which chip size i need - but i let you know about the outcome...  > spin PCMCIA hardware back in about a week ... but we were > planning on just the 16-bit PC Card implementation.  a 16 bit card should not be a problem. a co-worker designed such  card before he left us - he "forgott" to implement the cis - the card  works but everybody who has to use this card curses him ;-)

[Altera_Forum]

Stonie, 

 <div class='quotetop'>QUOTE </div>  --- Quote Start ---  If not - any suggestions for a different core (wchich costs less than $2000 on royalties).[/b]  --- Quote End ---   in my project I use the core from PLD-Applications (www.plda.com) . It&#39;s a Master / Target PCI / PCI-X core for 32 or 64 Bit bus-size. I&#39;ve implemented a PCI-target function, that has access to a shared SRAM on Avalon-Bus, which is the System-RAM. So, I have a small boot loader in EPCS, but the main firmware is loaded via PCI-bus direct into the SRAM (PCI-Space 0). Further I&#39;ve implemented a master function to transfer data from Avalon via PCI-DMA to the host PCI-Memory. And third, a bidirectional register file (PCI-Target) to communicate (PCI-Space 1).  I spent lots of time to implement the target interface PCI <-> Avalon: when PCI requests access to an Avalon device, a wait signal from Avalon is active while the arbitration process is working. If wait ends, the following single cycle is the access cycle to Avalon. But the PCI core needs after the delay phase several PCI-clock cycles until its own access will be processed. In other words, the PCI core expects, that he has got the system bus an indefinite time until its access is done. So this interface to Avalon is not adapted very well. With my interface only 32-Bit transfers are possible, because byteenables from PCI core are valid, several cycles after Avalon access is done.  Mike

[Altera_Forum]

MiR, 

 How much is this core? Do you have to pay one time royalties or is there a per part fee?  How long is the learning phase you needed for propper usage of this core?  Do you have any experience about their customer support?   I&#39;m sorry to ask these questions - but if i want to use a commercial core, i have to convince  my boss to spend some money for something which can be downloaded for free on opencores,  and in my opinion there are just 2 advantages of a commercial IP:  - customer support - the duration of the learning/debugging phase  Thank you for your time,  Klaus

[Altera_Forum]

Hi Klaus, 

 I didn&#39;t pay this core, but from our Distributor (EBV Germany) I&#39;ve got the info: about 1800 Euro for a project licence up to 5500 Euro for a full supported licence. You do not have to pay an extra &#39;per unit fee&#39;. But contact EBV for details.  No problems arose during developing the PCI side. I let quartus create a symbol of the top entity and connected this side 1:1 to the PCI connector. An utility from PLDA is used to configure the core (Vendor-ID, Memory Spaces, etc) . The only problem I had, was the interface to Avalon, and I&#39;m not yet satisfied with the results I&#39;ve got. I have to restrict access in target mode to be always 32-bits wide. But take a look at <pldas users guide> (http://www.plda.com/download/doc/ip/pci/user_guide.pdf) on page 16 / 17 what happens after inserting wait states to the PCI core. In some cases, this documentation should be more specific (" .. typical write transaction..")  I only have spare experiences with support. The company is located in france, anwers come quickly. I think, plda also provides an evaluation core. You should utilize this and invest one or two days to investigate the options you have.  Mike

[Altera_Forum]

Hi, 

 I&#39;ve used the PLDA master/target PCI core in a Nios Cyclone design.  Their support via e-mail is very good.  They also offer a free reference design (VHDL) for a PCI/Avalon bridge.  From personal experience I would not recommend using this reference  design, mostly because it is based on an older version of their PCI core which is not i/o compatible with later versions.  Alan

[Altera_Forum]

Hi , 

 I am using the PCI open core at the moment. I am wondering how to declare the avalon connection to it : memory or register, read latency, wait states... I want to access an external flash, an external RAM, an onchip memory and some external IOs... Can somebody help me ?. I am having problems as well to understand what image are for in the PCI opencores ???   http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif