Pausing target processor: not responding.????

Altera_Forum · ‎11-16-2005

hello,i have designed a cy12 nois board by myself,and i download the configuration file .sof to fpga is ok,but when i run a simple program in IDE the following message are:

Using cable "ByteBlasterII [LPT1]", device 1, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused

i am sure both the pin assignment and the program are right, and the board 3.3v and 1.5v is ok too,can everyone can help me? thank you!

Altera_Forum · ‎11-21-2005

If your design is complex (i.e. not a minimal system) then I would reduce it (especially any offchip memory/peripheral connections). Here's what I recommend:

Nios II 's' core (with a level 1 OCI core)

8kB of onchip memory

sysid peripheral

jtag uart

Then try running the hello world small software template on it. If that works then start adding offchip devices one by one to figure out which one is breaking your design. If the idea above doesn't work then I would dump an even simplier design in (like an AND gate) to see if that even works. If a dirt simple non-jtag communication design (no OCI, JTAG UART, or SignalTap II) works then I would start looking at your JTAG signals on the PCB for noise.

I hope that helps.

Altera_Forum · ‎11-24-2005

yes i did the simpest design ,the problem is the same,i think it maybe the noise problem,i am doing the second board ,thank you!