Performance Counter

Altera_Forum · ‎03-11-2005

I want to measure a time count taken for a section of a code. But the output i'm getting is always zero. I'm viewing my output through IDE output console.

I have patched my code and the output i got.

Note: Using Quarus II 4.2 SP1

Can anyone help me in this regard.

Thanks,

Sanchu.C

# #########################CODE#####################

# include <stdio.h># include "altera_avalon_performance_counter.h"# include "system.h"

void* perfbase = 0x00100800; # define COMPUTE_FUNCTION_SECTION 1

void compute()

{

int counter,sum;

sum=0;

PERF_BEGIN (perfbase, COMPUTE_FUNCTION_SECTION);

for(counter=0;counter<100;counter++)

sum=sum+counter;

PERF_END (perfbase, COMPUTE_FUNCTION_SECTION);

printf("\n Sum = %d \n",sum);

}

int main()

{

printf("Hello from Nios II!\n");

PERF_RESET (perfbase);

PERF_START_MEASURING (perfbase);

compute();

PERF_STOP_MEASURING (perfbase);

unsigned int section_time = 1;

section_time = perf_get_section_time (perfbase,COMPUTE_FUNCTION_SECTION);

printf ("section_time: %d\n",section_time);

perf_print_formatted_report(perfbase, ALT_CPU_FREQ,1,"compute");

return 0;

}

# ##################OUTPUT VIEW THROUGH IDE CONSOLE#####################

Hello from Nios II!

Sum = 4950

section_time: 0

--Performance Counter Report--

Total Time: 0 seconds (0 clock-cycles)

+---------------+-----+-----------+---------------+-----------+

+---------------+-----+-----------+---------------+-----------+

|compute | NaN| 0.00000| 0| 0|

+---------------+-----+-----------+---------------+-----------+

Altera_Forum · ‎03-15-2005

Found a workaround for this problem:

It seems to work fine if I take the Verilog project from Standard folder under \kits\nios2\examples\verilog\niosII_stratix_1s10\standard and add performance counter to it.

If I take Vhdl project from Standard folder under \kits\nios2\examples\vhdl\niosII_stratix_1s10\standard then, it is not working fine.

Altera_Forum · ‎03-29-2005

--- Quote Start ---

originally posted by sanchu@Mar 15 2005, 06:23 AM

found a workaround for this problem:

it seems to work fine if i take the verilog project from standard folder under \kits\nios2\examples\verilog\niosii_stratix_1s10\standard and add performance counter to it.

if i take vhdl project from standard folder under \kits\nios2\examples\vhdl\niosii_stratix_1s10\standard then, it is not working fine.

--- Quote End ---

I'm having the same problem... does anyone got it running using VHDL?

Paolo

Altera_Forum · ‎04-05-2005

yes for me it seem to work in vhdl,

i'm using the kit cyclone(EP1C20) from altera, with nios2.1 quartus 4.2 sp1.