Programming Board Flash

[Altera_Forum]

I am working on a project trying to develop some software on an Altera DE1 board. It is driven by a Cyclone II EP2C20F484C7 and first of all the SOPC Builder in Quartus II doesn't have a Board Description file for this board. However, that is not the main issue of this post, although it might be contributing to the problem. 

 The problem is that when we try to program the .sof file to our board via the Flash programmer in Nios II the following error message is produced in the build window # Error - Unable to locate a flash memory module name '' in the SOPC Builder system C:/altera/61/ip/sopc_builder_ip/altera_avalon_adapter_downstream_pipeline/class.ptf  We are wondering if this could be a result of not having a board description file for our board. We built our system in SOPC Builder as a "Custom" board and only specified that it was a Cyclone II. We put all the components into the system builder however I've read a couple places that if your using an altera nios dev board you must have a board description file specified. The CD that came with our board contained no such file and the closest description file available in SOPC Builder is for a Cyclone II EP2C35 device and again, not sure if that would be compatible since it's not technically our device.  If we have to make a board description file than ANY info on how to generate or find a netlist for our board would be great!  Any and all initial comments/thoughts/solutions to this problem are very welcome as anything you have to say may help my team and I try and figure this thing out thanks in advance!

[Altera_Forum]

In 6.1, you shouldn't need a board description file. Try using the IDE's Flash Programmer GUI and choose "custom" in order for you to be able to set the offsets within the flash. 

 - slacker

[Altera_Forum]

Well using the "Custom" area of the IDE's flash programming GUI we got past that hold up but now it's saying that it cannot find a CFI Table at address 0x00000000 

 The CFI flash base address in SOPC is locked at 0x00000000 and we have an offset in the IDE's flash programmer of 0xC00000 which is the default. Do we need to change the offset in the flash programmer or how do we get a CFI table at the base address?  Thanks for your help!

[Altera_Forum]

No.  

 The CFI table is accessed upon device initialization only. The fact that the flash programmer can't read it means that you likely have a hardware (board, SOPC Builder, or connectivity) issue.  Have you notified Terasic of this issue? If not, why don't you try that path in parallel with whatever sort of debug you're doing? Are you using an unadulterated example from them? If not, then I would make darned sure that you've done exactly what they did in their example!  I've not used this board, or I'd have more advice for you....sorry.  Good luck!  - slacker

[Altera_Forum]

Yep, solved that problem with a fix on pin assignments, but on to the next problem unfortunately.  

 When trying to write to our Flash now, we are getting a file size too large. There should be no reason that a 4M flash run out of memory on a simple Hello LED program. The FPGA configuration file is where it is saying it is too large, but the configuration we are using for the FPGA is a slightly modified version of one that came in the demonstration files. Our Base address starts at 0x00000000 and goes to 0x003FFFFF which is 4M. Any ideas would be helpful.  THANKS!

[Altera_Forum]

Please post your flash programming script (if using the IDE, it should be in the Debug or Release directory of your user project), and the error messages that you're seeing. 

 I'll see if I can help.  - slacker

[Altera_Forum]

As was said the flash chip is 4MB capacity... what is the script file's extension? I wasn't sure which one was the flash script file so I don't have that for you yet but here's an exact copy and paste from the Nios II console window: 

# !/bin/sh# # This file was automatically generated by the Nios II IDE Flash Programmer.# # It will be overwritten when the flash programmer options change.#   cd C:/DE1/DE1_demonstrations/DE1_NIOS/software/Media_Center_X/Release # Creating .flash file for the FPGA configuration "$SOPC_KIT_NIOS2/bin/sof2flash" --offset=0xC00000 --input="C:/DE1/DE1_demonstrat ions/DE1_NIOS/DE1_NIOS.sof" --output="DE1_NIOS.flash" Info: ******************************************************************* Info: Running Quartus II Convert_programming_file Info: Command: quartus_cpf --no_banner --convert C:/DE1/DE1_demonstrations/DE1_N IOS/DE1_NIOS.sof DE1_NIOS.rbf Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings  Info: Allocated 43 megabytes of memory during processing  Info: Processing ended: Wed Jan 31 16:42:59 2007  Info: Elapsed time: 00:00:03 # Programming flash with the FPGA configuration "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00000000 --cable='USB-Blas ter [USB-0]' "DE1_NIOS.flash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: Input file is too large to fit (device s ize = 0x400000) OK Leaving target processor paused # Creating .flash file for the project "$SOPC_KIT_NIOS2/bin/elf2flash" --base=0x00000000 --end=0x3fffff --reset=0x0 --i nput="Media_Center_X.elf" --output="cfi_flash_0.flash" --boot="C:/altera/61/ip/n ios2_ip/altera_nios2/boot_loader_cfi.srec" # Programming flash with the project "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00000000 --cable='USB-Blas ter [USB-0]' "cfi_flash_0.flash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK   : Checksumming existing contents   00000000 : Verifying existing contents   Checksummed/read 1kB in 0.0s  Erase not required  00000000 ( 0%): Programming   Programmed 1KB in 0.0s  No change to device contents Leaving target processor paused

[Altera_Forum]

You're trying to place the hardware at offset 0xC00000 when your device ends at 0x3fffff. That won't work. 

 What were the original settings for the "user" image? I'd imagine it's something like 0x200000 or 0x300000, but it should be mentioned in some of your DE1 documentation. Take a look through one of the PTFs for the included example designs for "user" and "factory" offsets.  Cheers,  - slacker

[Altera_Forum]

It&#39;s always that third party perspective kickin in to be able to point out a simple mistake or ommision http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif I am not in the lab right now to try that out and make sure it works but it definatly makes perfect sense and I am pretty sure that&#39;ll do the trick. 

 That&#39;s not to say there won&#39;t be more problems because at the rate we&#39;ve been going there&#39;s gonna be plenty more to arise. But at any rate thanks a million slacker you really helped keep us on track. Appreciate your help. Feel free to keep an eye out for future problems to pop up http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/tongue.gif   Thanks!

[Altera_Forum]

Can&#39;t seem to find any documentation on what to set the offset to, or the details on how it works. Does the offset designate a region in the flash for the FPGA hardware configuration, leaving the lower addresses for programmable memory? We have tried a bunch of different offsets, and had no luck. The .sof file is 465KB and the .flash is 1,188KB. We tried using a value of 0x1220A0 which corresponds to the .flash size. Also tried 0x200000 and 0x300000 and several values between. Any information on how the offset works would be good.  

 THANKS!  Here is a dump of the console with an offset of 0x1220A0: # Creating .flash file for the FPGA configuration "$SOPC_KIT_NIOS2/bin/sof2flash" --offset=0x1220A0 --input="C:/DE1/DE1_demonstrat ions/DE1_NIOS/DE1_NIOS.sof" --output="DE1_NIOS.flash" Info: ******************************************************************* Info: Running Quartus II Convert_programming_file Info: Command: quartus_cpf --no_banner --convert C:/DE1/DE1_demonstrations/DE1_N IOS/DE1_NIOS.sof DE1_NIOS.rbf Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings  Info: Allocated 43 megabytes of memory during processing  Info: Processing ended: Fri Feb 02 09:41:51 2007  Info: Elapsed time: 00:00:03 # Programming flash with the FPGA configuration "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00000000 --cable=&#39;USB-Blas ter [USB-0]&#39; "DE1_NIOS.flash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK   : Checksumming existing contents   00120000 : Reading existing contents   00130000 : Reading existing contents   00140000 : Reading existing contents   00150000 : Reading existing contents   00160000 : Reading existing contents   00170000 : Reading existing contents   00180000 : Reading existing contents   00190000 : Reading existing contents   Checksummed/read 37kB in 1.1s   00120000 ( 0%): Erasing   00130000 (12%): Erasing   00140000 (25%): Erasing   00150000 (37%): Erasing   00160000 (50%): Erasing   00170000 (62%): Erasing   00180000 (75%): Erasing   00190000 (87%): Erasing   Erased 512kB in 4.1s (124.8kB/s)   00120000 ( 0%): Programming   00130000 (12%): Programming   00140000 (25%): Programming   00150000 (37%): Programming   00160000 (50%): Programming   00170000 (62%): Programming   00180000 (75%): Programming   00190000 (87%): Programming   Programmed 476KB +36KB in 10.5s (48.7KB/s)  Device contents checksummed OK Leaving target processor paused # Creating .flash file for the project "$SOPC_KIT_NIOS2/bin/elf2flash" --base=0x00000000 --end=0x3fffff --reset=0x0 --i nput="Media_Center_X.elf" --output="cfi_flash_0.flash" --boot="C:/altera/61/ip/n ios2_ip/altera_nios2/boot_loader_cfi.srec" # Programming flash with the project "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00000000 --cable=&#39;USB-Blas ter [USB-0]&#39; "cfi_flash_0.flash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK   : Checksumming existing contents   00000000 : Verifying existing contents   Checksummed/read 1kB in 0.0s  Erase not required  00000000 ( 0%): Programming   Programmed 1KB in 0.0s  No change to device contents Leaving target processor paused

[Altera_Forum]

We did find out that u need a hardware description in SOPC Builder in order to program flash. In the process of getting that to work. Maybe thats why we couldn&#39;t write to the flash, dunno yet. Any help is still appreciated.

[Altera_Forum]

Please read the documentation....specifically the User&#39;s Guide that came with your board! 

 I just took a quick glance through it, and I don&#39;t even think that what you&#39;re trying to do is even possible. It looks like your board only boots out of an EPCS16 device.  So... as near as I can tell, your 4MB of CFI flash can be used for software (or other data), but not for an FPGA hardware image. Your hardware should always be stored in the EPCS16 device.  Cheers,  - slacker  EDIT: You _can_ program both the EPCS device and your CFI flash device with the flash programmer. Good news is that your flash programming is working....it&#39;s just that your board doesn&#39;t support (I don&#39;t think) what you&#39;re trying to do.