Programming .sof file with nios dev kit stratix

[Altera_Forum]

Hi. 

I've bought an Altera Nios development Kit Stratix edition, and I want to program my FPGA with a .sof file compiled from a .gdf file. I don't have any error messages neither while compiling, nor when I program. Loading executes fine, "user" led shines an instant, but just after, the FPGA comes back in his "safe" config, which was already running since power-on or reset. Does someone know where could be the problem, and how to solve it?? Is it due to the Nios core, which I don't need and which is running on the default configuration?? If someone has any suggestion, I'd be really helped. Thanks

[Altera_Forum]

The problem doesn't seem to be due to a loading failure, because the system runs when I program another nios config. So, must there be a nios core in any development programmed on this board??

[Altera_Forum]

Hi Ice_Tiss, 

It&#39;s a very strange situation. I think u could check if your project pinout uses pins of the development board that could cause the reset of the board.Sorry it&#39;s only an hint http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

[Altera_Forum]

I&#39;ve watched my prograzm but I didn&#39;t find any reset used pin. So I don&#39;t understant what happens. Even with a simple 8 bit counter, plugged on board&#39;s leds, the problem is the same.  

It seems like if my configuration is not correct and the factory configuration takes back the control. I really don&#39;t know what&#39;s going wrong!

[Altera_Forum]

Make sure that you have the Unused Pins for your Quartus project set to be Inputs Tristated. You can do this as follows after the project is opened in Quartus: 

 1. Click on Assign --> Device 2. Click on the Device and Pin Options Button 3. Click on the Unused Pins Tab. 4. This should be the first Radio button.  Just to elaborate on why this is:  A feature of the Nios development boards is to demonstrate remote reconfiguration. This is done via an FPGA I/O which is connected to the MAX CPLD on the board. The MAX CPLD is programmed to re-configure the FPGA when the signal is driven low (in this way, the FPGA can send a signal telling the MAX chip to reconfigure itself). For reference designs that include this pin and leave it high, or tri-stated, there is no issue. However, a user design must either drive this pin high manually, tri-state the pin manually, or leave the pin un-assigned and tri-state the unused outputs (as Subroto&#39;s instructions indicate).

[Altera_Forum]

I found!!!!! 

Visibly, there is a pin, on EP1S10 FPGA which must be set at VCC. it&#39;s the pin U2 named PLD_RECONFIGREQ_N in the examples. I don&#39;t know why, but once this pin set, the program remains active after the end of loading. I regret that this is not told in the board&#39;s datasheets, or if it is told, it is certainly lost somewhere in the 779 (or more!) datasheet pages!  Thanks guys for your help

[Altera_Forum]

I had the same problem. Thank you for the solution!! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

[Altera_Forum]

You&#39;re welcome MRks! 

 Now, if ever you find a solution that permits to load a .pof file, for having a non-volatile config, think to me, I haven&#39;t found yet! Thanks

[Altera_Forum]

PLD_RECONFIGREQ_N ...... unrolling the short forms: PLD_RECONFIGURATION_REQUEST_N. Now if you look at a schematic for a Nios development board your problem will make sense (find the device that signal connects to).

[Altera_Forum]

In fact, it&#39;s told in the nios Dev board manual that one way to start the configuration sequence is to "assert (driving 0 volts on) the MAX&#39;s reconfigreq_n input pin (from a stratix design). 

So I think holding this pin to Vcc might be a way to avoid it coming low after my config finished. But certa

[Altera_Forum]

Thanks 

In fact, it&#39;s written in the Nios Dev Board Manual that one way to start the configuration sequence is to "assert (driving 0 volts on) the MAX&#39;s reconfigreq_n input pin (from a stratix design). So I think holding this pin to Vcc might be a way to avoid it coming low after my config finished. Certainely not the best, but the way Jesse told me, which was setting unused pins to tristate wasn&#39;t efficient. (I don&#39;t understand why, because it sould have been!)  And if you have an idea for programing my config and get it reloaded after power-on (I thought programing .pof file), I would be really happy!  Have a nice day!