Qsys interconnect

[ASubr1]

I have a Nios II processor system with my own Qsys component which to monitor data memory access. The component has one slave (s1) (Nios data master is connected here) and one master (m1) (slave port of data memory connected here). So inside my component I just pass slave signals to master signals like shown below so that processor can access data memory as normal. (My program is running correctly)

               -- Pass the requests from CPU on to the memory

               avm_m1_address                               <= avs_s1_address;

               avs_s1_readdata                                 <= avm_m1_readdata;

               avm_m1_read                                      <= avs_s1_read;

               avm_m1_writedata                              <= avs_s1_writedata;

               avm_m1_write                                      <= avs_s1_write;

               avs_s1_waitrequest_n                       <= avm_m1_waitrequest_n;

               avm_m1_burstbegin                           <= avs_s1_burstbegin;

               avm_m1_byteenable                          <= avs_s1_byteenable;

               avs_s1_rdata_valid                              <= avm_m1_rdata_valid;

               avm_m1_burstcount                           <= avs_s1_burstcount;

And also inside my component I am counting number of data memory accesses made by the processor. But this counting seems like wrong. I am using this condition to count in every clock cycle: (clock is same for all)

rising_edge(clk) then

if (avs_s1_read = '1' or avs_s1_write = '1') and avm_m1_waitrequest_n = '1' then

Is this correct way to identify ONLY data memory access?

Processor data master is also connected to other slave as well (slave of system id, timer, jtag uart, instruction memory). How Qsys identifies the correct slave port? Using Destination_ID? Is it accessible? or invisible?

Next thing Qsys uses byte address. So we can’t restrict without knowing base address.

Thanks

[CheePin_C_Intel]

Hi, As I understand it, you have some inquiries related to the counting of data memory access by NIOs II using your custom component. If I understand it correctly, the avs_s1_read is the read signal and avs_s1_write is the write signal from NIOs II. By merely looking at the condition, there seems to be no anomaly. Would you mind to share further on the following: 1. Would you mind to share further on your counting code? The current code seems to show only the condition but not the counting portion? 2. Mind further elaborate on the counting wrong observation? Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[ASubr1]

Thank you for the response.

Yes, you understood correctly. 

signal count : integer;

signal clk : std_logic;

signal s_reset_n : std_logic;

signal s_cs_enable : std_logic;

signal r_temp_count : std_logic_vector(31 downto 0);

process(clk)

               begin

                               rising_edge(clk) then                                                    

                                              if avs_scon_write_n = '0' then

                                                              case avs_scon_address is

                                                                               when "000" =>

                                                                                               s_reset_n <= not avs_scon_writedata(0);

                                                                                               s_cs_enable <= avs_scon_writedata(1);                                             

                                                                               when others => null;

                                                               end case;

                                               else

                                                               case avs_scon_address is

                                                                               when "000" =>

                                                                                               r_temp_count <= std_logic_vector(to_unsigned(count,32));                                                                                    

                                                                               when others => null;

                                                               end case;

                                               end if;

                               end if;

               end process;

avs_scon_readdata <= r_temp_count;

process(clk, s_reset_n)

begin

if s_reset_n = '0' then

count <= 0;

elsif rising_edge(clk) then

if (avs_s1_read = '1' or avs_s1_write = '1') and avm_m1_waitrequest_n = '1' and s_cs_enable = '1' then

count <= count + 1;

end if;

end if;

end process;

To read /write my component I am using another port. The signals are shown below.

-- Slave port connecting to the controller CPUCON

avs_scon_address : in std_logic_vector(2 downto 0);

avs_scon_readdata : out std_logic_vector(31 downto 0) := (others => 'X');

avs_scon_read_n : in std_logic;

avs_scon_writedata : in std_logic_vector(31 downto 0) := (others => 'X');

avs_scon_write_n : in std_logic;

avs_scon_waitrequest : out std_logic := 'X'

I don't need to count all the portion of my program. So before start to count, I reset and enable. Then I am doing some read, write onto data memory using IOWR_32DIRECT and IORD_32DIRECT (now for testing purpose) . Then I disable. Manual counting and the expected output are different. It counts more.

Thank you

[CheePin_C_Intel]

Hi, Regarding your inquiry on how Qsys identify the specific slave, as I understand it, in the Qsys system, each component or slave will have a specific base address. Master will use the base address to identify the target slave. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[ASubr1]

Hi

Yes, Each component will have base address.

But when I examine address signal(avs_s1_address), it is byte address. So base address is invisible to us.?

Thank you

[CheePin_C_Intel]

Hi, You will need to know the base address from your Qsys system so that you can access them through NIOs II. Generally for accessing certain offset of a module, we will need to multiple the offset by 4 ie $base_addr + $offset * 4

[ASubr1]

Hi

Thank you for the response.

Yeah, but I didn't mean that here.

In my component, when I count, I am using conditions. At that point if I check the incoming address is within data memory address range, I could narrow down the extra counts. The address signal (avs_s1_address) coming from NiosII has only byte address. So if we can get base address signal also, we could figure out if any other address range is counted.

Thanks

[CheePin_C_Intel]

Hi, Thanks for sharing. As I look through the portion of code which do the counting, sorry as I am not able to spot any anomaly. To facilitate further debugging, I would recommend you to perform simple count ie one read or one write to see if your counter is able to capture it. Then slowly increase the number of read or write to see if can replicate issue. With simple count, this could help to narrow down unexpected read/write. Best regards, Chee Pin

[ASubr1]

Hi

Thank you for the response.

Yeah, When I increase slowly, at some point it counts 95 extra, for the further increments the count error is multiples of 95.

Another thing is, when I increase clock frequency, the 1st point is going back. It means it could count more read/writes correctly. For less clock frequency the error comes early.

Thanks

[CheePin_C_Intel]

Hi, Thanks for your update. For your information, based on the current observation, I think you would need to further debug into your counting algorithm to see if can spot any anomaly. I would like to suggest you to create a simple design or simplify your existing design by using on-chip memory. Then perform 100 writes to on-chip memory. You may write data 1 to 100 to the memory to ease debugging. You can read back the data to verify if data are written correctly to the memory. Signaltap the signals at the slave of your counting component, master of your counting component which connect to memory and the internal counters. Then perform a cross check among these signals and counter values to further narrow down the issue. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[ASubr1]

Thank you for the reply.

Yeah I am using simplified version for debugging process.

As I said earlier, my program works correctly, even simple read/write or any other huge program.

Only problem is counting. We should prevent the counting during the clock cycle when the processor master is occupied with other slaves.

Thanks

[CheePin_C_Intel]

Hi, Thanks for your update. Just wonder if you have had a chance to try signaltaping the signals at the interfaces of involved component to further narrow down the issue? thank you.

[ASubr1]

Hi

Thank You.

Yes. I Signaltap both input(avs_s1_address) and output(avm_m1_address) signals. Both are same.

And also I collected memory access traces.

For example program (given bellow), I access same memory location. But in the memory access traces, there are some other memory addresses. As I said earlier, for certain number of read/write, in the middle there are continues 95 extra addresses, when I increase read/write, I could see another same set of extra addresses.

counter_RESET();

counter_ENABLE();

while(IORD_32DIRECT(BASE, 8) < 30000){

IOWR_32DIRECT(BASE, 8, IORD_32DIRECT(BASE, 8)+1);

}

counter_DISABLE();

Where these accesses are coming from? (Only NiosII data master is connected to Data memory.) And how can I prevent counting these accesses?

Thank You

[CheePin_C_Intel]

Hi,

Thanks for your update. If I understanding it correctly, in your current simple test design, you have NIOs II -> Counter -> On-chip Memory. Just wonder if you have had a chance to signaltap the following during a write only process:

1. write from NIOs

2. write the On-chip Memory

You can then cross check if the write activities are tally. With this method, you could isolate the addressing from the debugging.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[ASubr1]

Hi

Thank You.

I checked signals of data master port at Nios, counter's slave & master and on-chip-memory's slave port. Yep all are same. Those extra addresses are coming to on-chip-memory.

But still couldn't find what they are.

And another thing, for the same program (even without compiling again), these extra address sometimes come sometimes don't.

Thanks

[CheePin_C_Intel]

Hi,

Thanks for your update. As I understand it from your latest observation, it seems like you are observing NIOs II intermittently feed additional address to on chip memory. For your information, I have duplicated a new case 04276053 to seek further assistance from NIOs II SMEs. I have informed respective team to expedite the case routing.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[CheePin_C_Intel]

Hi,

For your information, the new duplicated case seems to empty and the new AE is unable to view any details on it. To facilitate further discussion, I would like to seek your help to create a new case on the NIOs II intermittently feed extra address to on chip memory and let me know the case number so that I could help to route it accordingly. Sorry for the new inconvenience.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[Ahmed_H_Intel1]

Hi Arudchutha,

First of all, I see you can count the read/write via NIOS II by adding a PIO component from NIOS Qsys that goes up every write or read command happens, or to use the C-code in NIOS in counting the read/write executions.

One more thing, This might be a cash issue, i think you need to clear the On-Chip memory cash first to be sure that you see the correct count. I am not sure as I didn't see how you constructed your system, please correct me If I understood the issue wrongly.

In the new case you can mention my name while creation and I will be following with you this issue.

Regards,

[ASubr1]

Hi

Thank you for the response.

Actually my component is doing more using the data memory accesses at real time. For the debugging process I simplified as a simple counter.

I built a simple NiosII system with clk, id, timer, jtag uart, two onchipmemory (one for data memory and one for instruction memory), NiosII/f and counter. Accesses to data memory goes through counter.

NiosII/f settings: Reset vector memory: instruction memory offset:0

Exception vector memory: instruction memory offset:0x20

Instruction cache: 4Kbytes

Data Cache: None

Multiply/shift/Rotate Hardware: Auto selection

Include JTAG Debug

One more thing , now I could reduce those extra accesses from 95 to 9. When I create an application project using NiosII Software Build Tools, some settings I left as default. Now I changed these two to instruction memory : hal.linker.exception_stack_memory_region_name and hal.linker.interrupt_stack_memory_region_name. Now extra accesses are multiplies of 9.

Thanks

[ASubr1]

Hi

I could find that those unknown data memory accesses are because of Interval Timer interrupt. But I still wonder what hardware interrupt does with data memory even after changing interrupt_stack_memory_region to instruction memory. Anyway I could eliminate those extra accesses by preventing timer interrupt request for a certain portion of my program where I am taking data memory accesses.  But disabling hardware interrupts is not a good solution right? What are that read/write to data memory during timer interrupt? 

Thanks

[Ahmed_H_Intel1]

Hi,

Good investigation. Yes disabling hardware interrupts is not a good solution but this narrows down the issue to know the root cause. Did you check the interrupt configuration or use Vectored Interrupt controller VIC instead to see if the same issue exists?

Thanks