Register view

[Altera_Forum]

I noticed that while stepping thru some assembly, I could not alter the outcome of a cmpge if I changed one of the register values just before the compare. I thought I would be able to do this, particularly on an e core. This brings up the question of how the debug interface is tied into the different processor cores. How is normal execution altered (pipeline, etc) while stepping?

[Altera_Forum]

Now I see. You have to use sign extended values for these compares.  

 The question about pipeline is still valid. Does running under the debugger basically disable any pipeline?

[Altera_Forum]

When you are single-stepping it appears as though the pipeline is disabled. 

In the Nios II/s and Nios II/f, multiple instructions are dispatched into the pipeline when single stepping but only the first is allowed to complete. The other instructions are flushed before modifying any programmer-visible state. The Nios II/e doesn't really have a pipeline so it is in a sense always single stepping.