Running from ex sram

[Altera_Forum]

Hi, 

my custom board is now working with the exception of the NIOS. I can run the prog from external 16bit sram via JTAG, no problem.  But when I use the flash programmer the nios will not boot. The logic runs fine, but the cpu is dead.  Am I missing anything basic here?   Agdepus   ************************************************** Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK  : Checksumming existing contents  00000000 : Verifying existing contents  00010000 : Verifying existing contents  Checksummed/read 112kB in 3.3s  Erase not required 00000000 ( 0%): Programming  00010000 ( 0%): Programming  Programmed 112KB in 0.0s  No change to device contents Leaving target processor paused ************************************************** Then I flip the power.....nothing

[Altera_Forum]

You didn't mention how you're programming the flash...command line or via the IDE. Also, when booting from the EPCS you must set the reset address (in SOPC Builder) to the small onchip memory (which is part of the EPCS component). 

  Cheers,  - slacker

[Altera_Forum]

The reset address points to the base of the epcs controller. 

 I am using the flash programmer ide. 6.1. Getting desperate here, has to work tomorrow......  Here's the flash prog log:  # !/bin/sh# # This file was automatically generated by the Nios II IDE Flash Programmer.# # It will be overwritten when the flash programmer options change.#    cd Z:/Projects/Projects2006/DNP2006007-NorhtMarker/Logic/DNP2006007_2_0/software /PRIB3_NorthMarker_1_0/Release  # Creating .flash file for the FPGA configuration "$SOPC_KIT_NIOS2/bin/sof2flash" --epcs --input="Z:/Projects/Projects2006/DNP2006 007-NorhtMarker/Logic/DNP2006007_2_0/DNP2006007_2_0.sof" --output="DNP2006007_2_ 0.flash" Info: ******************************************************************* Info: Running Quartus II Convert_programming_file Info: Command: quartus_cpf --no_banner --convert --device=EPCS64 --option=DNP200 6007_2_0.opt Z:/Projects/Projects2006/DNP2006007-NorhtMarker/Logic/DNP2006007_2_ 0/DNP2006007_2_0.sof DNP2006007_2_0.pof Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings  Info: Allocated 54 megabytes of memory during processing  Info: Processing ended: Wed Jan 10 16:43:19 2007  Info: Elapsed time: 00:00:08 Info: ******************************************************************* Info: Running Quartus II Convert_programming_file Info: Command: quartus_cpf --no_banner --convert DNP2006007_2_0.pof DNP2006007_2 _0.rpd Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings  Info: Allocated 49 megabytes of memory during processing  Info: Processing ended: Wed Jan 10 16:43:27 2007  Info: Elapsed time: 00:00:08  # Programming flash with the FPGA configuration "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --epcs --base=0x00022800 --debug -- verify "DNP2006007_2_0.flash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK Processor data bus width is 32 bits Looking for EPCS registers at address 0x00022800 (with 32bit alignment)  Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A  Not here: reserved fields are non-zero Looking for EPCS registers at address 0x00022900 (with 32bit alignment)  Initial values: 92400237 4A40100C 483FFD26 90000135 92400237 4A40200C  Not here: reserved fields are non-zero Looking for EPCS registers at address 0x00022A00 (with 32bit alignment)  Initial values: 00000000 00000000 00000260 00000000 00000000 00000001  Valid registers found EPCS signature is 0x12 EPCS identifier is 0x202013 Using EPCS size information from section [EPCS-202013] Device size is 0MByte (4Mbit) Erase regions are:  offset 0: 8 x 64K EPCS status is 0x00   Verifying 00000000 ( 0%) Verifying 00010000 (57%) Verified 112KB in 0.0s  Leaving target processor paused  # Creating .flash file for the project "$SOPC_KIT_NIOS2/bin/elf2flash" --epcs --after="DNP2006007_2_0.flash" --input="P RIB3_NorthMarker_1_0.elf" --output="epcs_controller.flash"  # Programming flash with the project "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --epcs --base=0x00022800 --debug -- verify "epcs_controller.flash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK Processor data bus width is 32 bits Looking for EPCS registers at address 0x00022800 (with 32bit alignment)  Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A  Not here: reserved fields are non-zero Looking for EPCS registers at address 0x00022900 (with 32bit alignment)  Initial values: 92400237 4A40100C 483FFD26 90000135 92400237 4A40200C  Not here: reserved fields are non-zero Looking for EPCS registers at address 0x00022A00 (with 32bit alignment)  Initial values: 00000000 00000000 00000260 00000000 00000000 00000001  Valid registers found EPCS signature is 0x12 EPCS identifier is 0x202013 Using EPCS size information from section [EPCS-202013] Device size is 0MByte (4Mbit) Erase regions are:  offset 0: 8 x 64K EPCS status is 0x00   Verifying 0001BEF3 ( 0%) Verified 8KB in 0.0s  Leaving target processor paused

[Altera_Forum]

I checked the output of the flash programmer and it seems perfectly OK (no changes to the Flash content since a previous attempt already succeeded). 

 Are you trying to run a hello world that uses the jtag_uart, it the board is not connected to a PC and the Jtag-uart terminal is not running, a printf to the jtag-uart will halt the execution of the software.  IzI

[Altera_Forum]

Oooops, 

just found out that the flash programmer does not work at all. I assumed it deleted the EPCS before programming it.  Instead, the image programmed via quartus still sits there ....(assumed the EPCS got cleared before reprogramming it)  Did a dump via command line, the HW image programmed by flash programmer is not there. despite verify ok..........  If I do a JIC programming via the SFL then i can dump the config data.....  suggestions?

[Altera_Forum]

Check your reset circuitry, if you have none, add a reset button with a debouncer. I have recently had reset problems (maybe a problem in the PLL stability) and I had to extend my reset delay from 2ms to 500ms. Before my software was running fine after I pushed the reset button, but the software (uCLinux) crashed after the power up. 

 IzI

[Altera_Forum]

I managed to get the program to boot from internal ram. That is good enuff for now. 

But I cannot believe that Altera hasn't released simple howtos in this area. Spending days reading docs instead of developing is a waste of time.... We did wrote our own lessons learned and compiled them into the ERM's, so hopefully we will remember to look there the next time... Which is stratix II.......  Should I post it here?  Thanks all...

[Altera_Forum]

You should use less tla (http://en.wikipedia.org/wiki/tla), I do not understand most of them. It seemed to me that booting from flash was pretty straight forward. If you find time to explain what your problem was and how you solved it, it will be appreciated. 

 IzI