Running from on-chip memory.

[Altera_Forum]

I have been trying for several days to get a custom board to run Nios II embedded processor with a hello world program with no luck. I have successfully achieved this task with evaluation kits, but so far not with my board. I have searched this forum and tried several things that I saw, but I had no luck. 

 My board is about as simple as they come. A Cyclone, EPCS4, and oscillator with both an active serial programming header and JTAG header (pulled directly from the Altera manual). I have used the FPGA for other tasks (so the board works), but I have only just started trying the Nios processor.  My current SOPC configuration is:  - Nios II/s with debug level 1 running at 50Mhz. - UART - JTAG UART - On-chip Memory configured as ROM - On-chip Memory configured as RAM - EPCS Controller  In the FPGA configuration, I have a PLL taking 25Mhz and upping it to 50Mhz for the clk line of the processor. I have all the pin assignments set to output pins with the exception of the reset_n line which is set as an input pin normally vcc.  In the Nios IDE (v5.1), I have setup a "hello world small" program. The system library is set to output stdin/out/err to the jtag uart and the rom gets the text and the read-only info, while the ram gets the read-write/heap/stack info.   I program the FPGA configuration and then perform a "run as hardware" in the IDE and everything goes with no errors. I am expecting to see the hello world output in the terminal, but I don't. Sometimes I get a series of ascii characters like the baud rate is wrong, other times I get nothing. I have tried changing my clock speed with no luck.  I tried to add some serial uart code from a previous (known good) program to see if it was just bad JTAG communication. It seems that the program is not running at all. No serial activity at any baud rate...  I do see the rom and ram *.hex files being created. I have tried to recompile the FPGA configuration and re-program the FPGA but the program doesn't run. How can I verify that the new *.hex files were included in the configuration?  I have tried:  - changing the clock input speed (lower and higher than 50Mhz) - various memory configurations (started with a single on-chip memory) - various hello-world programs (stand alone, small, normal, etc) - to get debug info going through the UART - looked at the clock input on an external IO and it is there - to change the reset address to the EPCS - and more.  I must be missing something simple.  Can anyone give me any ideas? I am running out of hair to pull out!   Thanks  Chris Lathan

[Altera_Forum]

We were just having the same issue and found that the program was hanging in alt_main because of problems initializing the flash. 

 Click Run/Debug... Click the Debugger tab, and on the right hand side you can tell the debugger to break at alt_main. This lets you see how the initialization progresses. I suggest stepping into alt_sys_init() to see which individual init functions run successfully.  This should help narrow the problem down. For me, the program hung when initializing the flash. Just to get up and running, I commented the line initializing the flash in the Altera-generated code. After that, all systems were go.  Good luck!  Dave

[Altera_Forum]

I am working toward a solution. I haven't completely defined the problem I was having, but I was able to get the program to run. 

 It turns out that I had a mistake in my SOPC configuration. The on-chip memory I allocated was too large but I never got any error from the fitter in Quartus.   Something I did made the error appear. This gave me something to chase and fix. I finally found the memory size that would fit and run the program and everything ran fine from there.   The only change I made was an order of operation change. I was running from SOPC-Quartus-IDE but when I changed to SOPC-IDE-Quartus, the error appeared.  I had compiled the FPGA configuration probably 30 times with no sign of an error. Of course I can't repeat it now. I change my order of operation back to SOPC-Quartus-IDE and all is fine.  I guess I was just too dependent on being told something was wrong...  Thanks for the help.  Chris

[Altera_Forum]

1) Make sure the program fits into the ROM files 

2) Once the ROM files have been written, you have to recompile and reprogram the PLD from Quartus.