SDRAM access speed?

Altera_Forum · ‎12-15-2005

Using Nios II & SOPC builder, I'm trying to design an DMA to SDRAM interface that will transfer data from an on chip ram to SDRAM using DMA.

I used ModelSim to test my interface and found that I can have an SDRAM access speed of ~40MB/s. Have anyone been able to go at a higher access speed than that?

I have done many things to make the speed faster and allow larger transfer of data trunk. I set the SDRAM controller clock and SDRAM pll to 75 MHz (tried 80 but failed). My DMA controller and on chip ram clock is set at 100 MHz. The arbitration# between DMA and SDRAM is set at 64.

Also, my on-chip ram size is set to 16KB and DMA's length is 16.

Does anyone have any other suggestion that will allow me to speed up the SDRAM access speed? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

Thanks a ton for your reply...

Altera_Forum · ‎12-21-2005

--- Quote Start ---

originally posted by quin_crc@Dec 15 2005, 12:28 PM

using nios ii & sopc builder, i'm trying to design an dma to sdram interface that will transfer data from an on chip ram to sdram using dma.

i used modelsim to test my interface and found that i can have an sdram access speed of ~40mb/s. have anyone been able to go at a higher access speed than that?

i have done many things to make the speed faster and allow larger transfer of data trunk. i set the sdram controller clock and sdram pll to 75 mhz (tried 80 but failed). my dma controller and on chip ram clock is set at 100 mhz. the arbitration# between dma and sdram is set at 64.

also, my on-chip ram size is set to 16kb and dma's length is 16.

does anyone have any other suggestion that will allow me to speed up the sdram access speed? http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/unsure.gif

thanks a ton for your reply...

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=11589)

--- quote end ---

--- Quote End ---

Sorry about unable to answer your question. But want ask you how did you get on-chip RAM address mapped onto avalon bus. I am proposing to transfer more than 10K memory contents to SDRAM by DMA. Thanks a lot, and sorry for bothering.

Altera_Forum · ‎12-22-2005

Are you using the PLL output directly to the SDRAM clock? I think you must screw it by a few degrees relative to your NIOS clock. From what I can remember some of the example designs demonstrates this.

VictorS