SDRAM clock?

[Altera_Forum]

Dear everyony, 

I use 50M main clock in my nios2 system, but I want to use 100M clock to my SDRAM ,which is 16 bit interface, to enhance the SDRAM performance!    Is it ok? and what should I pay more attention to when use like this?    Best Regards!  Fei Wu

[Altera_Forum]

--- Quote Start ---  originally posted by feiwu@Apr 27 2006, 01:37 AM dear everyony,         i use 50m main clock in my nios2 system, but i want  to use 100m clock to my sdram ,which is 16 bit interface, to enhance the sdram performance!           is it ok? and what should i pay more attention to when use like this?                  best regards!         fei wu <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14742)  --- quote end ---    --- Quote End ---    50MHz main clock means your low level I/O is driven at this frequency. Exchanging data between parts running at different speed, FIFO should be considered. As I understand...

[Altera_Forum]

As far as i understand the avalon switch fabric this should not be the user&#39;s problem but in fact it is handled by the clock domain crossing section of the avalon switch fabric. 

 You can run nios cpu at a different clock speed than all the other sopc modules.  place a fast clock wherever you need fast clock and a slow clock at sopc modules like uart that do not need to run at the fast clock.  you can place some pll&#39;s that produce different clocks and connect the sopc modules as you like.  we (the user) do not have to worry about clock domain crossing as this is handle by quartus.   but .. i have to report that a simple nios_cpu + sdram @ fastclock and even a sysid @ slowclock with one sopc_pll delivering both clocks didn&#39;t work here and nioscpu was not able to read the sysid. But no time yet to do more investigation about that.  Regards.  Michael Schmitt

[Altera_Forum]

Thank you very much for your reply! 

  now I use the sharded date/address bus,so can&#39;t use the different clock!   So I download a Twister DDR SDRAM controler from www.fpga.nl , Had everyone ever used it sucessfully?   Could the DDR SDRAM enhance the system performance?    by the way, why the 32M byte-32bit-Tsop(Package) SDRAM would be end of life?  I have search hynix,samsung,micron,winbond etc., only FBGA package 32bit is available?   Best Regards  Fei WU

[Altera_Forum]

Last year Micron recommended us to use the MT48LC8M32B2F5-7IT that is now obsolete and has its last time buy. So we deceided to go back from bga (32bit) to tsop (16bit). but it seems that we will go another step to bga (16bit) 

 Also we did the decision last year to use Micron MT28F256J3FS-12_ET Flash to have Intel J3 Strata as second source, but both are also obsolete by now.  I wonder why the manufactures / distributors give recomendation when those parts get obsolete so sooooooon.  Regards.  Michael Schmitt

[Altera_Forum]

Just a note about clock-domain crossing.. first, it adds a lot of logic to your design, and therefore compile time. If you can afford this, then you should note that clocking your RAM higher than your CPU will only yield marginal results - not linear. Using burst-capable components, such as RAM cores, (I don&#39;t even think SDRAM bursts that well - DDR is a bit better) may not take advantage of the higher clock speed.