SDRAM verify failed in NIOS II IDE

[Altera_Forum]

I work under QII5.0. My SDRAM is Micron MT48LC2M32B2-7. 

I choose the "single Micron MT48LC2M32B2-7 chip" in the "presets" of sdram controller setup menu. My SDRAM base address is 0x00800000. When I run my project in NIOS II IDE, the message is  Using cable "ByteBlasterII [LPT1]", device 1, instance 0x00 Pausing target processor: OK Reading System ID at address 0x02000810: verified  Downloading 00800020 ( 0%) Downloaded 1KB in 0.0s   Verifying 00800020 ( 0%) Verify failed  Leaving target processor paused  What is wrong? Someone can help me?

[Altera_Forum]

The nios core and SDRAM peripheral operates (samples) on rising clock edges. SDRAM clocks out data on rising edges (valid on falling edges). If you do not run the SDRAM clock through a PLL to tweak phase shifting, it will not work. If your SDRAM is very close to the FPGA, you can get away with using an inverter (180 degrees). I have done that up to 96 MHz. If you have more than 2cm of distance between the SDRAM and FPGA, you will have to use the PLL and tweak the clock using an oscilloscope. Have you tried using the FS2 console to modify SDRAM contents?

[Altera_Forum]

This could be a general hardware failure as well. Check your I/O to make sure it is assigned properly and that you have unused I/O being automatically set to what you need for your particular board (usually tristate). Are you targetting a custom board or a Nios development board?

[Altera_Forum]

I had to add pull up 1K on CS and OE on my SRAM to make them work, maybe you must do something like thatas well.

[Altera_Forum]

--- Quote Start ---  originally posted by albs@Jul 1 2005, 12:49 PM the nios core and sdram peripheral operates (samples) on rising clock edges.  sdram clocks out data on rising edges (valid on falling edges).  if you do not run the sdram clock through a pll to tweak phase shifting, it will not work.  if your sdram is very close to the fpga, you can get away with using an inverter (180 degrees).  i have done that up to 96 mhz.  if you have more than 2cm of distance between the sdram and fpga, you will have to use the pll and tweak the clock using an oscilloscope.  have you tried using the fs2 console to modify sdram contents?  --- Quote End ---   http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif thank you so much!!Indeed the pll is necessary when you add a sdram to your system~

[Altera_Forum]

Yes, I have use PLL to compensate the phase shift. 

 I use Mtx Cyclone Board. I have read the DataSheet of the board. The sheet says  "The clock driving the SDRAM is based on the 32.768MHz on-board oscillator (no multiply or divide), and is delayed by 27ns before being sent to the SDRAM component. This allows a 3-4 ns delay for the SDRAM clock to arrive at the chip, which in turn allows the SDRAM access to occupy the entire 30.5 ns clock period if needed."  The Phase shift is 318.51 in 32.768MHz. I use PLL to generate the 49.152MHz Clock, the 1.5 times board clock. So I set 18ns in the clock phase shiht tab. But IDE displayed verify failed.

[Altera_Forum]

--- Quote Start ---  originally posted by liangyi@Jul 4 2005, 03:04 AM yes, i have use pll to compensate the phase shift.  i use mtx cyclone board. i have read the datasheet of the board. the sheet says  "the clock driving the sdram is based on the 32.768mhz on-board oscillator (no multiply or divide), and is delayed by 27ns before being sent to the sdram component. this allows a 3-4 ns delay for the sdram clock to arrive at the chip, which in turn allows the sdram access to occupy the entire 30.5 ns clock period if needed."  the phase shift is 318.51 in 32.768mhz. i use pll to generate the 49.152mhz clock, the 1.5 times board clock. so i set 18ns in the clock phase shiht tab. but ide displayed verify failed.  --- Quote End ---   On myself cyclon board(ep1c6t144c8),no delay,the sdram can also work for read\write but didn&#39;t run program on sdram.when I set -72 dgree on sdram clock(about 4 ns),It runs well.

[Altera_Forum]

I want to know if the phase shift is same in different frequency. 

In my board, there has no frequency test-point, but I want to test the delay, how can I do?

[Altera_Forum]

I have solved my problem. 

I use PLL and try to set the Phase Shift Value according to the datasheet. Finally, the sdram is running Ok.