SPI master with DMA controller

[Altera_Forum]

Hi everybody! I need to implement an spi link beetwen a cyclone4 (master) and a spartan3a (slave) fpga. I would like to implement a DMA base solution where the master reads continuously data from slave and save this data in ram. Actually I have a working solution without DMA but I want to free NIOSII from this task. My idea is NIOSII operates on other tasks and everytime it needs of data from spartan3a it can read ram location where DMA engine write. I think this is possible and maybe quite easy but I don't be able to find enough information to do it by myself...if someone could help me... 

 I use a DBC4CE55 board, this code read continuously 32 bit from spi slave and show on leds a part of these 32 bit received data.   int main() {  alt_u32 *response_packet=0;   while(1)  {  alt_avalon_spi_command(SPI_BASE, 0, 0, NULL, 1, response_packet , 0);  IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE, *response_packet>>3);  }   return 0; }   Now I have added a DMA controller in my qsys design and connect it to spi core...for the software side I have many doubts...is there any examples? Thanks

[Altera_Forum]

Better use SPI to Avalon-ST core and connect it to SGDMA (Stream to Memory). You'll get interrupt when transfer is done.

[Altera_Forum]

Ok, thank you for the answer I understand SGDMA is better for my application. However SPI to Avalon-ST core is a slave core and I need the master one so I have to implement my own SPI master to Avalon-ST core.

[Altera_Forum]

I have a similar configuration. I am building it using DMA instead of SGDMA. I would like to know how different is between SGDMA and DMA. I realized in SOPC, SGDMA has more connections, which I have no idea to connect them. Thank you.

[Altera_Forum]

--- Quote Start ---  I have a similar configuration. I am building it using DMA instead of SGDMA. I would like to know how different is between SGDMA and DMA. I realized in SOPC, SGDMA has more connections, which I have no idea to connect them. Thank you.  --- Quote End ---     Hi Waiyung, _matt_,   I am trying to use SPI core in conjunction with DMA controller on Cyclone IV. Did anyone of you try the same and able to achieve it? I am newbie to this field. I have the qsys design which has NIOS II and SPI core at this moment. With this, I am able to read and write the bytes. Now, I would like to use DMA controller with SPI to send and receive the bytes without intervening the NIOSII.   I would be glad, if you can help me with some tips or examples to further proceed with this design. Please let me know if you have any link or design examples which can give more insight to me on this. Thanks in advance.  Regards Pavan