SRAM interface timing parameters

[Altera_Forum]

I'm currently setting up my NIOSII system on my own board. 

I've done some measurements on the SRAM_nCS, SDRAM_nWE... signals. I find the timing a little bit too tight.  It seems like it is not possible to change this in the SOPC builder??  How can I modify these timings?  Kind regards,  nvdb

[Altera_Forum]

Please clarify: SRAM or SDRAM?

[Altera_Forum]

oeps, 

 it's sram and NOT SDRAM; signals should be SRAM_nCS, SRAM_nWE...  Kind regards,  nvdb

[Altera_Forum]

Here's what I got from one of the developers. Please tell me if it helps you solve your problem... 

 The default dev kit SRAM component (two IDT71V416 chips, normally appearing as &#39;ext_ram&#39; in example designs) should automatically compensate for timing by adding appropriate Avalon wait states depending on the desired System Clock Frequency.  Internal memories do not compensate in the same way; other external memories require their own class.ptf files to configure their timing requirements.  You cannot modify the timing settings of the default component -- it does all the math for you, based on System Clock and it&#39;s class.ptf settings. There are 3 sets of settings (wait states & setup/hold times), for the following frequency ranges:  {f <= 50MHz}  {50MHz < f <= 100MHz}  {f > 100MHz}   To get different setting requires making your own component/class.ptf, or hand editing the system.ptf.

[Altera_Forum]

Thanks for your reply! This was the answer for my question; I&#39;ve tried it in hardware and it&#39;s working. 

 Bye.

[Altera_Forum]

Great! 

Happy NiosII-ing http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif