Sharing Bus

[Altera_Forum]

I have a 1C20 dev board and find out some details. It has two SRAMs and one 16MB SDRAM and SRAM & flash & LAN share address bus and data bus. Compared with SDRAM, SRAM has smaller capacity and bigger power dissipation. I just wonder why it adopts SRAM instead of just using SDRAM. 

On the 1C20 development board, SDRAM occupies so many pins, why not let it share data bus or address bus with other devices?  Thanks.

[Altera_Forum]

1) SDRAM is a complex beast. It contains volatile memory and needs to be refreshed on a periodic basis. Also you have to clock in commands and 2 sets of addresses, column and row. The SDRAM contoller is always busy accessing the memory for refreshing so there are no real quiet times to share with other devices. So this cannot easily be shared on a bus. 

2) Flash, SRAM and LAN contain simple interfaces. To write data to SRAM you place an address, data word and strobe a write command. Also the SRAM is non-volatile as long as power is applied, so you don't have to refresh it. This means that there is a lot more quiet time on this bus. Only one device is active at a time. You will either talk to the SRAM, Flash or LAN, never more than one at the same time.   The kits come out with all these so you can develop on a wider range of options.  1) SDRAM is cheaper (for me here in South Africa). You get much more bytes for your buck. Although it runs theoretically slower than SRAM you can clock it faster. I have applications where a tweak or two levels the playing field. There is also more development in the field of SDRAM. Just have a look at your PCs memory and the speeds those chips are running. You will, in the case of NIOS, always (probably) have to use a bigger FPGA. 2) SRAM is more expensive per byte, but very simple to use. You will use these on simpler designs where you don't need large memory capacities. I have a design infront of me running NIOS1 with 128k of SRAM, 1MB Flash, LAN, 2 x 8 bit DACs, 2 relay outputs, 2 inputs, HTRC110 proximity card interface, Dallas RTC, Dallas WDT, 2 UARTS, 2 LEDs plus a few spare pins all packed in on a 1C3 144pin device. If I added SDRAM the chip would probably have been a 1C6 240 pin device.  You can probably write a core that has SDRAM and SRAM/FLASH/LAN on the same bus (using some fancy footwork interleaving refresh cycles inbetween) but I don't think you will save that much. Probably will require more gates and a bigger device.   So the use will be application specific.  VictorS

[Altera_Forum]

So,has anybody implemented the "share bus" with various of periperials, such as SDRAM, Flash, Ethernet, SRAM....? If yes, it will encourage me to do the same!

[Altera_Forum]

My CPU (NIOS II/s 1.1 in a Cyclone EP1C12/7) uses: 

 - SRAM (256k x 32) on Avalon Tri-State - 3 different interfaces to user logic on Avalon Tri-State - 1 SDRAM-Controller sharing Address- and Databus (16MB) - 15 additional devices (ports, uart, spi) connected to Avalon-Bus - 2 further Bus-Master accessing SRAM and SDRAM (DMA and PCI-Bus)  Meanwhile it runs; after updating SDRAM-component from version 5.0 and decreasing CPU-clock down to 50MHz (Timing Analyzer says fmax=50,8 MHz). An interface to Ethernet (LAN91C111) is also connected to Avalon-Tri-State, but not yet tested. Booting is done via EPCS which also starts a small loader. The final firmware runs in SRAM, which will be loaded via PCI-bus -> Avalon-Master -> SRAM. With SOPC-builder 1.1 you have to manually edit the .pdf file, to get shared write_n and read_n signals.  eltonlaonong,  I use SRAM to get the performance and SDRAM to get the buffer size I need. Not sharing signals would allow you to do things real parallel (e.g. DMA transfer parallel to processing). But the pins ....  mountain8848,  encouraged enough?  Mike

[Altera_Forum]

very very romantic! 

   I am layouting the similar board, and will post the result later on!