Simulating NiosII Design in ModelSim \ Active-HDL with breakpoints

[Altera_Forum]

Hey everyone! 

 I want to simulate my NiosII software built with NiosII IDE with a simulation software (ModelSim \ Active-HDL). I've done some research over several sites and doesn't find any information about simulating the sofware with break-points like i've done on my target board with the same software. If I can't perform a simulation with breakpoints the whole thing is worthless cause it's impossible to debug the software without them. Can anyone know how can I do that? Is it even possible?  By the way, I can't find any updated Altera tutorial concern simulating the NiosII embedded software on model-sim, if anyone has one I would appreciate sending it to me.  Thanks in advance, Omri.

[Altera_Forum]

This forum will not let me post the link until I have at least 5 post or something. So I will just describe where you can find solution.  

 Please go to Aldec website and search NIOSII. There is a nice app note for Aldec Active-HDL. This app note describes how to simulate NIOSII design in Active-HDL.

[Altera_Forum]

I'll post the link for you: 

 http://www.aldec.com/en/support/resources/documentation/articles/1157 (http://www.aldec.com/en/support/resources/documentation/articles/1157)  (http://www.aldec.com/en/support/resources/documentation/articles/1157)

[Altera_Forum]

Thanks for posting the link.

[Altera_Forum]

Thanks for the kind replies! 

I've red all of the articles in Aldec website, but didn't find the exact answer about breakpoints in the simulation (only prints). Thanks in advance, Omri.

[Altera_Forum]

I would respectfully question why you really need to simulate breakpoints at all. The JTAG/debug interface is more or less a closed system, not even accessible in an RTL simulation. If you're talking about simulating the JTAG commands to set and clear breakpoints in a gate-level simulation, this would be so slow and unwieldy I'm not sure what you'd gain from it. 

 A long time ago I tried to do something similar to help with a problem I was having in a Xilinx design, but it really turned out that your best friend in debugging JTAG issues is an oscilloscope and a schematic.   Maybe you could describe exactly what you would be trying to achieve with this kind of simulation - maybe I'm missing the point.

[Altera_Forum]

Hey kebmsmith. 

The general idea is to integrate the HDL modules & software in the simulation level, before running it on board. If I want to check the compatibility of the SW & HDL I have to run the software process by process, checking it step by step, and by inserting breakpoints in the SW I can do this. I don't want to check the JTAG communication with CPU... I just want to check the functionality of the SW in convenient way in the simulation (breakpoints).  Thanks for your kind help, Omri.

[Altera_Forum]

--- Quote Start ---  Hey kebmsmith. The general idea is to integrate the HDL modules & software in the simulation level, before running it on board. If I want to check the compatibility of the SW & HDL I have to run the software process by process, checking it step by step, and by inserting breakpoints in the SW I can do this. I don't want to check the JTAG communication with CPU... I just want to check the functionality of the SW in convenient way in the simulation (breakpoints).  Thanks for your kind help, Omri.  --- Quote End ---    Ok, I'm not trying to grill you, just trying to understand how this would work. If you're not going to talk to the debug module via JTAG, how do you intend to set and clear breakpoints? And what advantage does this have over just having the software set/clear GPIO to communicate with the test bench and simulation environment?   Repectfully, -- Kevin

[Altera_Forum]

Define and clear breakpoints in the set of code before running modelsim. 

And yea, one way is to set a "breakpoint_pio" communicates with TB and when rises the TB stops, it's nice idea but I would be happier to more intuitive way for doing this and see the assertions in the SW code, like a breakpoints, I'm just realy currious why Altera didn't support this feature in the Nios simulation.