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Slow clock domain peripheral generating interrupt for a fast clock domain Nios takes too long to clear.

New Contributor II

​A Qsys custom peripheral is running at 33MHz and generates an interrupt that goes to a Nios runnign at 99 MHz. The Nios then has to clear the interrupt by writing to a register in the custom component. However, it will take several 99MHz clock cycles before the interrupt source is deasserted as it is running at a slow clock. This can cause the ISR to be reexecuted sometimes. What is the solution to this problem in Qsys?

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I see you can create an external block like an RTL block running at high clock frequency to be as a bridge between them to take the interrupt from your custom peripheral and send to NIOS, once the NIOS execute the interrupt and writes to the register the RTL block de-assert the interrupt as it is running in a high clock frequency.

You can also check the VIC Victor Interrupt controller IP in Qsys.



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