Surprised to get "converted into an equivalent circuit" warning

Altera_Forum · ‎12-01-2010

Hi Folks-

I have a Verlog delay line module that seems straightforward and seems to work when I simulate it using ModelSim and when realized on my Cyclone II FPGA. I always get warning 13310 for every bit in the delay line array:

 
Warning (13310): Register "MPS_SOPC:inst|pulse_engine_0:the_pulse_engine_0|pulse_engine:pulse_engine_0|sample_delay:delay|mem" is converted into an equivalent circuit using register "MPS_SOPC:inst|pulse_engine_0:the_pulse_engine_0|pulse_engine:pulse_engine_0|sample_delay:delay|mem~_emulated" and latch "MPS_SOPC:inst|pulse_engine_0:the_pulse_engine_0|pulse_engine:pulse_engine_0|sample_delay:delay|mem~latch"

Can anyone tell me what I can do to resolve this warning? Is this warning significant?

Here's the HDL code:

 
`define BUFFER_SIZE 64
 
module sample_delay(
  input wire reset_n, // Reset
  input wire adc_clock, // Sample clock
  input wire  adc_data, // Input sample
  output wire  adc_data_delayed // Delayed sample
);
 
  reg  mem;
  integer i;
 
  initial
  begin
    for(i = 0; i < `BUFFER_SIZE; i = i + 1) mem = 14'd0;
  end
 
  assign adc_data_delayed = mem;
 
  always @(posedge adc_clock or negedge reset_n)
  begin
    if(~reset_n)
    begin
      for(i = 0; i < `BUFFER_SIZE; i = i + 1) mem <= adc_data;
    end
    else
    begin
      mem <= adc_data;   // <--- COMPLAINS HERE AND NEXT LINE
      for(i = 1; i < `BUFFER_SIZE; i = i + 1) mem <= mem;
    end
  end
 
endmodule

Thanks for the help.

John Speth

Altera_Forum · ‎12-01-2010

curious why reset sets all registers to adc_data instead of 0. Cyclone II doesn't have both async preset and reset. changing adc_data to 14'd0 will suppress the warning

Altera_Forum · ‎12-01-2010

i think the power-up values from the initial block disagree with the values from your reset, causing the latch. this is why changing the reset values from adc_data to 0 fixes the issue

Altera_Forum · ‎12-01-2010

Apart from what's already said, your design forces the compiler to use a huge amount of logic cells for the delay array. By restructuring the code in an intelligent way, it can be realized as circular buffer in embedded dual-port RAM. The shift register MegaFunction does just this.

Altera_Forum · ‎12-01-2010

i can do this

Altera_Forum · ‎12-01-2010

--- Quote Start ---

i think the power-up values from the initial block disagree with the values from your reset, causing the latch. this is why changing the reset values from adc_data to 0 fixes the issue

--- Quote End ---

Thanks. That was the key to making the warnings go away. I'm amazed at the deductions that Quartus is making when it analyzes the HDL code. I wonder if it ever misses the intent.

My inexperience is obviously exposed. It's such a complex tool and there is clearly no substitute for experience and knowledge. I hope to acquire both over the years.

Thanks to everyone for your opinions and help.

JJS

Altera_Forum · ‎12-01-2010

Maybe sligthly Off Topic but I strongly disagree with the use of the "initial" statement for synthesizable designs.

Don't you think this is a dangerous way of describing circuits?

Altera_Forum · ‎12-01-2010

--- Quote Start ---

Maybe sligthly Off Topic but I strongly disagree with the use of the "initial" statement for synthesizable designs.

Don't you think this is a dangerous way of describing circuits?

--- Quote End ---

I half agree with you. Before I started this thread, I was told by a local expert (and believed it) that the "initial" statement was not synthesizable but useful for simulation. Based on that understanding, I leave the "initial" statements in so I can resimulate if necessary. I assumed it had no effect on synthesis.

The comments in this thread have shown me that the "initial" statement does have some indirect bearing on how the tool behaves. It might not make a bit of difference in the final synthesized output though. I have no idea how to prove or disprove that.

JJS