The NIOS II doesn't reply.

Altera_Forum · ‎07-03-2006

Hello,

everytime I want to connect to my NIOS II via the ByteBlaster cable (at my LPT port) the following messages appears in the NIOS II IDE

Using cable "ByteBlasterII [LPT1]", device 1, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused

The FPGA is successfully programm with the NIOS II design and the FPGA works fine, if I program it with some "by-hand-made" designs.

What do I do wrong? The design in the SOPC Builder contains just the CPU a onchip memory and the JTAG UART; nothing more, and I can't persuade it to work. :-(

Can someone help me?

Thanks.

Altera_Forum · ‎07-06-2006

Hello,

Two things come to mind at the moment regardinging your problem.

1) Debug Core: Make sure that you have added a debug core to your processor in SOPC Builder. This is done through the Nios II editor (double-click on the cpu in the table). If you don't have a debug core for the processor, then you're out of luck. I can't remember if the Nios II IDE will tell you this, however. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

2) Open Core Plus: If you are using an unlicense (evaluation) version of the Nios II core, make sure that you leave the open-core dilalog box running in Quartus. This message box will appear after you download the compiled SOF file to your board if it contains a Nios II processor. Don't click "cancel" on this message box if you intend to debug your system!!

Hope one of these solutions helps. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

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originally posted by grubenkarlo@Jul 3 2006, 08:57 AM

hello,

everytime i want to connect to my nios ii via the byteblaster cable (at my lpt port) the following messages appears in the nios ii ide

using cable "byteblasterii [lpt1]", device 1, instance 0x00

pausing target processor: not responding.

resetting and trying again: failed

leaving target processor paused

the fpga is successfully programm with the nios ii design and the fpga works fine, if i program it with some "by-hand-made" designs.

what do i do wrong? the design in the sopc builder contains just the cpu a onchip memory and the jtag uart; nothing more, and i can't persuade it to work. :-(

can someone help me?

thanks.

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