Trigger DMA by User Logic

[Altera_Forum]

Hi guys, 

 does somebody know if it is possible to trigger a DMA via User Logic?  My system now:  I have a User Logic (FIFO) that generates a IRQ. The NIOS starts the DMA to get the data from the FIFO to internal memory.  The system I would like to have http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif :  User Logic triggers DMA to copy data.   regards revolt

[Altera_Forum]

Hi Revolt, 

I&#39;ve made it. I think what you need a smart peripheral that inizialize your DMA to trasfer data. I&#39;ve designed it with a Avalon master port connected to the slave control port of the DMA;furthermore my smart peripheral has a slave port too, connected with Nios II processor, used to inizialize my peripheral...

[Altera_Forum]

Hi Soin, 

 thanks for your answer. Your solution sounds really interesting.   Do you configure the whole DMA with your peripheral or do u just set the "go" Bit?  regards revolt

[Altera_Forum]

Hi Revolt, 

I configure the whole DMA: readaddress,writeaddress,length and control. Initially Nios II processor writes some register of my peripheral to set some address...then it works by its own driven by an input interupt signal for each trasfer...

[Altera_Forum]

Revolt, 

I&#39;ll assume that the reason your current implementation (IRQ triggers Nios to set up the DMA transaction) isn&#39;t sufficient is because the interrupt latency is too long. If so, you could solve the problem in a different way, using Avalon flow control (formerly called "streaming").   Here&#39;s how it would work: you would give your FIFO had an additional output signal of Avalon type dataavailable. The DMA would immediately read from the FIFO whenever that signal was asserted. You could assert dataavailable on ~fifo_empty, or do something more complicated with hysteresis on the number of words in the FIFO. It would still be up to the Nios to initialize each DMA transaction, but perhaps that could be done at a less time-critical point.  Try looking up dataavailable in the Avalon bus specification for more details.  Other possible solutions: 1) Create a dual-port memory peripheral with two slaves - one is a conventional memory interface, the other is a FIFO interface. Whatever is filling your FIFO in your current implementation can just write into the onchip memory directly, through the FIFO interface. 2) Put an Avalon master interface on your FIFO component - have that master write into the onchip memory whenever it needs to.

[Altera_Forum]

@Kero: 

Yes, u are right. I want to aviod the interrupt latency. I&#39;ll have a look at your suggestions.  Thanks a lot.