Triple Speed Ethernet and transceiver blocks

[Altera_Forum]

We have a Nios2/s processor running a triple speed ethernet (TSE) with a scatter gather DMA. Working off the of the triple speed ethernet example from altera for our board (DE4 Stratix IV board), there seems to be a missing option. When setting up the TSE, the option "Use Transceiver Block" does not exist, though all other settings match. Our system can send but is not receiving properly. What does this option do? Is there a new setting that replaces this option? (We are using a later version of Quartus than the example used). 

 This is the only salient difference we can currently find between our design and the example. What could be causing this issue?  Thank you in advanced.

[Altera_Forum]

Did not know that Terasic's TSE ref design uses transceivers. you don't need transceivers for TSE. 

BTW each devkit reference design is fine tuned to a specific Quartus version. So use the proper Quartus version.

[Altera_Forum]

I think transceivers are used when connecting to a PHY though a SGMII interface. This is only possible with FPGA's that actually have transceivers, so the option is greyed out for the other FPGA families.

[Altera_Forum]

Stratix IV GX EP4SGX230 does have transceivers.

[Altera_Forum]

my bad, I thought it was a regular Stratix 4. 

In that case, can you check that the target for the TSE core is indeed the correct FPGA family. I just created a test project with a Stratix 4 GX and I had no problem checking the "use transceiver block", as long as the TSE type that I selected was "10/100/1000Mb Etheret MAC with 1000BASE-X/SGMII PCS"