Software version : Quartus V 4.2 SP1
Nios II Development Kit - Stratix Edition 1S10
Device : EP1S10F780C6
Using the 'Create New Component' interface we have managed to create a peripheral that has both Master and Slave ports. This component has been found to work correctly through functional simulations , however the same system fails to work on the board . Here is the problem .
On writing into successive locations within the slave and subsequently trying to read from those locations it seems as if IDE hangs (in the RUN mode ).
In debug mode IDE gives the following error " Watchdog has expired - Target detached " on reaching the line that reads locations within the slave.
Using signal tap analyzer we have realized that the processor issues the read request for the first address and the RAM inside the slave does respond with valid data however we do not see the processor issuing a request for the next address to be read .
PS: We have been observing this problem ever since we migrated to Q 4.2 from Q4.0 . On Q 4.0 the Master Slave component was created by manually editing class.ptf file and the problem we faced was different in the sense that that the output from the board was different from the expected output , again RTL simulation was fetching correct results on Q 4.0 also )
Any thoughts ??
