Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

Upgrade via Ethernet

Altera_Forum
Honored Contributor II
1,237 Views

http://www.altera.com/literature/an/an346.pdf (http://www.altera.com/literature/an/an346.pdf) is a reference document about upgrade thru Ethernet link. I'm looking how to do that with more details. 

 

Thanks, 

Oleg K.
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
536 Views

I had the same task and been through all these files and doc from the altera web site. Thanks to the fae for their great support. 

 

Now this is done and the result is an max2 EPM570F100 that does the cfi flash access and fpga init. it does first try to upload the user image with a couple of retries and then load a fail safe image. after configuration the max2 releases the cfi that nios2 can access it. there is also the possability for a reconfig to both images, a watchdog that boot's the oposit image and an spi interface for accessing the 512bytes flash the max2 has over nios2. 

 

Yes this all fits into this device but i had used the full device. 

Q2 reports :  

Device : EPM570F100I5 

Total logic elements 570/570 (100%) 

Total pins 76/76 (100%) 

UFM blocks 1/1 (100%) 

 

The FPGA EP2C50 is configured with 24MHz DCLK Speed at 48MHz external clock speed. 

 

The implementation is very easy. 

But watch out, be aware of the timings you have to look after and that the fpga can request a restart.  

 

Regards. 

 

Michael
0 Kudos
Altera_Forum
Honored Contributor II
536 Views

Hi Mike, 

I have a design without this configuration chip. Is it some way to use SRAM and FLASH only?  

 

Oleg.
0 Kudos
Altera_Forum
Honored Contributor II
536 Views

Hi Oleg, 

 

i am quit not shure about your target design. 

Does ist consist : 

 

FPGA 

Flash 

SRAM 

Ethernet (for example) 

 

and what source of your fpga image (inside Flash oder epcs) ? 

 

Of you have an epcs then you can of course update your epcs via nios, but no fall back option if update is corrupted 

 

if you have the image inside a flash then you need some kind of external configuration device that reads out the image from the flash an stores it into the fpga. 

 

Regards 

 

Michael
0 Kudos
Altera_Forum
Honored Contributor II
536 Views

The target board has everything (SRAM, FLASH, ethernet, FPGA, serial EEPROM) like reference board except MAX config chip.

0 Kudos
Altera_Forum
Honored Contributor II
536 Views

ahhh okay ... 

 

then you should be able to update the serial config device via nios. 

 

you have ethernet, memory, nios ... and hopefully a running system. 

but if your update of the serial device fails and you try to restart, do not have a running system and need a blaster. 

 

regards.
0 Kudos
Reply