User Configuration Ignored

[Altera_Forum]

Hi Folks, 

 I'm just starting with the NiosII StratixII development board.  I've created a small design and downloaded it from Quartus 6.0 to the board. The User led blinks. The Loading led blinks. I expect my configuration to run.  But then the factory led starts blinking and loading and then the factory configuration starts running.  Is there something I'm missing about how to configure the FPGA so that the board recognizes a valid user configuration? I'm getting no errors or warnings when I program the part.  Thanks!  Ray

[Altera_Forum]

--- Quote Start ---  originally posted by rdsalemi@Dec 15 2006, 10:24 AM hi folks,  i&#39;m just starting with the niosii stratixii development board.  i&#39;ve created a small design and downloaded it from quartus 6.0 to the board.  the user led blinks. the loading led blinks.  i expect my configuration to run.  but then the factory led starts blinking and loading and then the factory configuration starts running.  is there something i&#39;m missing about how to configure the fpga so that the board recognizes a valid user configuration?  i&#39;m getting no errors or warnings when i program the part.  thanks!  ray <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20057)  --- quote end ---    --- Quote End ---     Check your pins settings (in Quartus), I&#39;m suspecting you have unused I/O set to ground (default). There is a pin between the FPGA and CPLD called reconfig request which is active low. So if you don&#39;t have that pin in your design when the FPGA comes up that pin is grounded which tells the CPLD to reprogram the device. In the example designs the pin settings for unused I/O has been set to input tri-state so that if that pin is unused it will be pulled up.