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User Logic interfacing?

Honored Contributor II

I'm just starting to try to integrate some user logic with a NiosII core. I have read round this  

quite a bit, including searching here but still have a few questions. 


I have the following interfaces at the top of my module that I need the CPU to be able to read and 

write to.. 


din : in std_logic_vector(15 downto 0); -- writedata 

wr : in std_logic; -- write 

op_enable : in std_logic; -- writedata 

op_polarity : in std_logic; -- writedata 

int_en : in std_logic; -- writedata 


empty_flag : out std_logic; -- readdata 

empty_intrpt : out std_logic; -- irq 

buffer_size : out std_logic_vector(9 downto 0) -- readdata 



I have tried integrating this using the 'Interface to User Logic' Legacy component, defining each interface as above. 

I have 6 read or write elements, but when SOPC builder created the component it only allocated 4 addresses 

for the component.  


Has it lumped ports into the same address? (As an aside, I presume it's more efficient for me to concatenate 

signal lines internally and provide fewer interface ports allowing the SW to identify the relevant bits). 


How do I know what's been allocated to which address? 


I'd like the interrupt to be edge triggered. When adding a PIO port you're given the option to select how the 

interrupt is raised. How is this defined for user logic? 



Thanks for any help with this, the documentation covering this doesn't seem clear and consise, and what 

there is is scattered far and wide (cue someone to post a link to an easily found idiots guide to user 

logic interfacing). 



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