Using EPCS on power up for uClinux

[Altera_Forum]

Hi, 

I have problems using the epcs as the boot device for the zimage file made with uclinux - the SW .   i have followed the instructions here : http://www.nioswiki.com/operatingsystems/uclinux/flashprogrammer   i have stratix II custom board and i am using quartus 7.2. my nios CPU has epcs controller, sdram and more. the reset address points to the epcs controller.   my design already worked without trying to boot from epcs ( meaning downloading via nios2-download and nios2-terminal).     after i program the epcs with the .flash files i am generating from the sof and the zimage as described in the nioswiki guide, nothing happens and the cpu isn't working when i power-up the board. the SOF file is working on the board but the OS (zimage file) isn't doing what it needs to do.   1. how can i debug this procedure?    2.boot loader file - the nios wiki tells you to use the  boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srec but i don't understand how could it not be changed after each  compilation. I mean - isn't this file dependent on my design??    3. shouldn't I change nothing on the design in my uClinux kernel?    4. what is the purpose of the file : epcs_controller_boot_rom.hex ?   Thanks,   Erez

[Altera_Forum]

Hi Dan, 

 I'll address your questions, one at a time:    --- Quote Start ---  1. how can i debug this procedure?  --- Quote End ---  Usually, you don't have to.    --- Quote Start ---  2.boot loader file - the nios wiki tells you to use the   boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srec  but i don't understand how could it not be changed after each   compilation.  I mean - isn't this file dependent on my design??  --- Quote End ---  No. This is a generic boot copier. The ELF file (even if it's a whole kernel) is translated into memory section based boot records consisting of a 32-bit word for copy location/address, a 32-bit word for size, followed by the data that needs to be copied....repeating for each memory section that requires copying.    --- Quote Start ---  3. shouldn't I change nothing on the design in my uClinux kernel?  --- Quote End ---  You shouldn't have to change anything.    --- Quote Start ---  4. what is the purpose of the file : epcs_controller_boot_rom.hex?  --- Quote End ---  That's the boot copier when using EPCS devices. EPCS devices are really just serial flashes, so a small onchip memory (epcs_controller_boot_rom) houses the boot copier code.  Have you tested that this boot procedure works on something simpler than uClinux/Linux? I would try a simple "hello world" and/or LED flasher before before something as large as a full kernel.  Cheers,  - slacker

[Altera_Forum]

Hi, 

Thanks Slacker, I have gotten confused about the procedure the sof and the software (zimage) are taken out from the epcs untill the software is running from the sdram or other ram devices. ( like the reset address purpose and the way the cpu starts from the sdram...) i would appriciate making some order in the mess.   Thanks, Erez

[Altera_Forum]

Hi Erez, 

 The SOF contains the "bitstream" that configures the FPGA. For systems that boot out of the EPCS, you point your CPU's reset address at the epcs_controller. Now, on boot, here's what happens:  1. The FPGA is configured from the data at the beginning of the EPCS device (by default). 2. Once the design starts running, the CPU loads the boot copier from the onchip memory contained in epcs_controller_boot_rom. 3. The boot copier copies the software from the EPCS device (section-by-section) into volatile RAM. 4. The last boot record tells the boot copier where to begin executing code in RAM.  That's it...  Cheers,  - slacker

[Altera_Forum]

--- Quote Start ---  4. The last boot record tells the boot copier where to begin executing code in RAM.  --- Quote End ---  1. Sorry, i missed something...where is this boot record taken from?  2. Is step number 4 done manually by enabling the command nios2-terminal ?  (manually booting using JTAG UART )  3. when booting from EPCS, JTAG UART should be disabled in kernel, right?  Thanks, Erez

[Altera_Forum]

1. There is a hidden onchip_mem inside the epcs controller. The onchip_mem content initialized in sof will be your reset vector as you defined to reset from epcs controller in sopc builder. Please check the boot loader sources at 

 /opt/altera9.0/nios2eds/components/altera_nios2/boot_loader_sources  2. nios2-terminal has nothing to do with booting.  3. You can still use jtag uart with "Bypass output when no connection" in uart config. Or you can use serial uart, ie RS232C.  - Hippo

[Altera_Forum]

Erez, 

 With respect to# 1, the "boot records" are created by elf2flash and reside in EPCS (in your case). The onchip memory which is part of the epcs_controller contains the boot copier code for the Nios II. This is why you point the Reset Address of your CPU (in SOPC Builder) at the epcs_controller component.  I hope that explains it. You have to keep in mind that an FPGA is a "blank slate" prior to being programmed/configured. Once you program it with your SOPC Builder design containing a Nios II processor, the processor will attempt to start fetching code from its Reset Address just after the FPGA is programmed.  Cheers,  - slacker

[Altera_Forum]

Hi, 

it's working now ! found the problem; when using the ptf on linux ( make vendor hwselect ), I chose executing from the epcs and not from the sdram ( of-course...)   Bless you all :-) Erez